Rambus Inc.

Nvidia Corporation

Velio Communications, Inc.

The University of North Carolina at Chapel Hill

Lsi Logic Corporation

Rumbus Inc.

John Wood Poulton

William James Dally

Frederick Abbott Ware

Robert E Palmer

Ramin Farjad-Rad

Thomas Hastings Greer

Andrew M Fuller

Jared L Zerbe

Scott C Best

Brian S Leibowitz

Kevin S Donnelly

Fred F Chen

Teva J Stone

John M Wilson

Sanquan Song

Thomas H Greer, Iii

Carl William Werner

Andrew P Ho

Carl Thomas Gray

Stephen G Tell

Walker Joseph Turner

Brucek Kurdo Khailany

Hiok-Tiaq Ng

Xiaoying Yu

Jonah Matthew Alben

Sudhir Shrikantha Kudva

Vladimir Marko Stojanovic

Andrew C Ho

Matthew Rudolph Fojtik

Mahmut Ersin Sinangil

Steven E Molnar

Nikola Nedovic

John H Edmondson

Xi Chen

John G Eyles

Ian P Shaeffer

Jade M Kizer

Lei Luo

Ephrem C Wu

Ge Yang

Reza Navid

Henry Fuchs

John Cronan Eble, Iii

Wayne D Dettloff

Brian Matthew Zimmer

Donald A Priore

John Eble

Ahmed Abou-Alfotouh

Olakanmi Oluwole

Kun-Yung (Ken) Chang

G E (Francis) Yang

Yoshinori Nishi

Wenxu Zhao

Arijit Banerjee

John Gordon Eyles

Steven Edward Molnar

Brian Lebowitz

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

High-speed signaling systems with adaptable pre-emphasis and equalization

A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

Configurable, power supply voltage referenced single-ended signaling with ESD protection

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Memory controller operable in data loop-back mode

A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.

Simultaneous bi-directional hybrid transceiver for single-ended voltage mode signaling

A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

Maintenance operations in a DRAM

The disclosure provides a signaling link that overcomes or at least reduces the limitations of RC-dominated signaling wires, improving both the bandwidth and the power consumption of signaling circuits. Both an AC and a DC signaling link are disclosed. In one example, a signaling link is provided that includes: (1) a transmitter including a passive equalizer, (2) an over-terminated receiver, and (3) a lossy channel having a first end connected to the passive equalizer and a second end connected to the receiver, wherein the lossy channel has a channel characteristic impedance that is lower than a terminating impedance of the passive equalizer and a termination impedance of the receiver.

Signaling over RC-dominated transmission lines

In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

Forwarding signal supply voltage in data transmission system

Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.

Level-conversion circuits for signaling across voltage domains

A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.

Memory controller with looped-back calibration data receiver

A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

CMOS signaling front end for extra short reach links

Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.

Low-power dynamic offset calibration of an error amplifier

Voltage level conversion circuits include PMOS pull-down devices or NMOS pull-up devices, and inverters with outputs that determine gate voltages of these devices. The inverters are powered by moving supply voltages, for example complementary supply voltages generated from a pair of cross-coupled inverters. The cross-coupled inverters may implement a data storage latch with the moving supply voltages generated from the internal data storage nodes of the latch.

Level-conversion circuits utilizing level-dependent inverter supply voltages

Growing community of inventors

Chapel Hill, NC, United States of America

John Wood Poulton