International Business Machines Corporation

John William Zack

Mark R Beckenbaugh

Michael D Cesky

Nicholas G Young

Jan Elizabeth Hoffman

Hubert Harrer

Zhaoqing Chen

Stephen Bruce White

Thaddeus Chen

Jay A Lawrence

Susan Marie Karwoski

Joonsuk Park

Jason J Freerkesn

Kenneth Lee Christian

Laura Marie Zumbrunnen

Scott Trcka

Michael Robert Curry

Richard Scott Brink

Edwin Scott Reichmann

Lily L Wang

Thomas C Perez

Jacqueline Denise Cromity

Lawrence Wayne Wood

Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations.

Categorization of design rule errors

In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined. A cost is assigned to each placement, the cost indicating an amount of jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater jog would be created in the masking process than would be created by a placement assigned a lesser cost. A placement having a lowest cost of the plurality of possible placements is selected.

Auto-routing small jog eliminator

A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a width difference between a width of the wire and a width of the source, and dividing the width difference by the width of the wire; and modifying a size of the wire if the first size differential is less than a maximum width percentage and if a length of the source is less than a length range specified by a user.

System and method for auto-routing jog elimination

A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a first width difference between a length of the wire and a width of the source, and dividing the first width difference by the width of the source; detecting a second size differential between the wire and the source if the first size differential is less than a maximum length percentage by calculating a second width difference between the width of the source and a width of the wire, and dividing the second width difference by the width of the source; and modifying a size of the wire if the second size differential is less than a maximum width percentage.

In an embodiment, data models are stitched into a stitched data model, where each of the data models has nets and at least one of the nets crosses a package boundary. A subset of the nets from the stitched data model are selected based on a constraint, and the subset is stitched into a common rule. In various embodiments, the constraints may include a wire length, a name of the nets, and maximum numbers of vias or T-connections. If the nets are completely wired, then wire segments between nodes of the nets are connected and nodes that include non-branching vias are moved. If the nets are not completely wired, then for any of the nets that have an open connection, a rule is found with a same number of the nodes as the net with the open connection, and the nets are ordered based on the rule.

Generating rules for nets that cross package boundaries

A method, apparatus and program product oversee and coordinate the automatic generation, monitoring and submission of package files and other modeling processes to enable focused, flexible and efficient modeling of design performance characteristics.

Simulation management system

A method, apparatus and program product generate package files that are separately stored and selectively combined to generate a net file suited for system simulation and analysis. Selective combination of the package files using respective reference connections of each package enables focused and efficient modeling of design performance characteristics.

Electronic circuit design analysis system

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Rochester, MN, United States of America

John William Zack