Intel Corporation

John William Phillips

Rahul Saxena

Nazar A Zaidi

Elango Ganesan

Michael Y Chow

A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, processing the input to render an arithmetic result. If the processor is in a second mode, performing a token specific operation. And producing an output. The present invention also provides a processor comprising a first instruction set engine, a second instruction set engine, and a mode identifier. A plurality of floating-point registers are shared by the first instruction set engine and the second instruction set engine. A floating-point unit is coupled to the floating-point registers. The floating-point unit processes an input responsive to the mode identifier and the input to produce an output.

Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support

A method for distinguishing an ordinary binary floating point number from an extraordinary binary floating point number is provided, the method including adding 1 to a B-bit biased exponent of a binary floating point number to produce a (B&plus;1)-bit augmented exponent and sign-extending the augmented exponent to produce a (B&plus;n)-bit transformed exponent. The method also includes testing the (B&plus;n)-bit transformed exponent to determine if the (B&plus;n)-bit transformed exponent is less than 2.

Converting between different floating point exponent representations

The present invention is a method and apparatus for rounding a result operand of a floating-point (FP) operation which causes an underflow. The FP operation is recomputed using a truncate rounding mode to generate an underflowed operand. The underflowed operand is denormalized and providing characteristic bits. A rounding bit is generated based on the characteristic bits. The rounding bit is merged with the denormalized operand to generate the rounded result operand.

Optimized rounding in underflow handlers

The present invention is a method and apparatus for reporting exception in a single instruction multiple data (SIMD) processor in computing an arithmetic function for a plurality of argument data. The SIMD processor is configured for processing N elements simultaneously. A sequence of instructions is re-arranged to allocate the plurality of argument data in the N elements. The N elements are processed simultaneously. The exceptions for N elements are detected simultaneously. The detected exceptions are then combined to generate a global exception.

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Menlo Park, CA, United States of America

John William Phillips