Skyworks Solutions, Inc.

Sige Semiconductor, Inc.

Other

Microsemi Semiconductor Ulc

Electrophotonic-ic Inc.

John William Mitchell Rogers

Mackenzie Brian Cook

Darren Roger Frenette

Ardeshir Namdar-Mehdiabadi

Alexander John Heaslip Ross

John Jackson Nisbet

Hassan Sarbishaei

Calvin Plett

Rachel Katumba

Brendan J Korba

Gordon Glen Rabjohn

Krste Mitric

Gudmundur A Hjartarson

William A Hagley

Lawrence E Tarof

Guohui Situ

Tuoxin Wang

An optical receiver comprises a monolithically integrated pin photodiode (PIN) and transimpedance amplifier (TIA). The TIA comprises InP heterojunction bipolar transistors (HBT) fabricated from a first plurality of layers of an epitaxial layer stack grown on a SI:InP substrate; the PIN is fabricated from a second plurality of layers of the epitaxial layer stack. The p-contact of the PIN is directly connected to the input of the TIA to reduce PIN capacitance C. The TIA capacitance Cmay be matched to C. Device parameters comprising: a thickness of the absorption layer, window area, and an optional mirror thickness of the PIN; device capacitance C+C; and feedback resistance Rof the TIA; are optimized to performance specifications comprising a specified sensitivity and responsivity at an operational wavelength. This design approach enables cost-effective fabrication an integrated PIN-TIA, for applications such as a 1577 nm receiver for an ONU for 10G-PON.

Optical receiver comprising monolithically integrated photodiode and transimpedance amplifier

Apparatus and methods for oscillation suppression of cascode power amplifiers are provided herein. In certain implementations, a power amplifier system includes a cascode power amplifier including a plurality of transconductance devices that operate in combination with a plurality of cascode devices to amplify a radio frequency input signal. The power amplifier system further includes a bias circuit that biases the plurality of cascode devices with two or more bias voltages that are decoupled from one another at radio frequency to thereby inhibit the cascode power amplifier from oscillating.

Apparatus and methods for oscillation suppression of cascode power amplifiers

Doherty power amplifiers with coupled line combiners are provided herein. In certain embodiments, a power amplifier system includes a carrier amplifier having a carrier output that provides a first radio frequency signal, a peaking amplifier having a peaking output that provides a second radio frequency signal, and a coupled line combiner including a first conductor line connected to the peaking output, a second conductor line electromagnetically coupled to the first conductor line, a third conductor line connected to the carrier output, and a fourth conductor line electromagnetically coupled to the third conductor line and in series with the second conductor line. The power amplifier system further includes an inductor in series with the fourth conductor line and the second conductor line and operable to provide a radio frequency output signal to an output terminal.

Doherty power amplifiers with coupled line combiners

Doherty power amplifiers with coupled line combiners are provided herein. In certain embodiments, a power amplifier system includes a carrier amplifier having a carrier output that provides a first radio frequency signal, a peaking amplifier having a peaking output that provides a second radio frequency signal, and a coupled line combiner that combines the first radio frequency signal and the second radio frequency signal to generate a radio frequency output signal at an output terminal. The coupled line combiner includes a first conductor line connected between the peaking output and a reference voltage, a second conductor line electromagnetically coupled to the first conductor line, a third conductor line connected between the carrier output and the reference voltage, and a fourth conductor line electromagnetically coupled to the third conductor line and connected between the output terminal and the second conductor line.

A power amplifier including a cascode output stage, a bias circuit, and a temperature compensation and bias boost circuit. The cascode output stage has an input and an output and includes first and second transistors connected in series. A base of the first transistor is coupled to the input, an emitter of the first transistor is coupled to a reference potential, a collector of the first transistor is coupled to an emitter of the second transistor, and a collector of the second transistor is coupled to a supply voltage and the output. The bias circuit is coupled to the base of the second transistor. The bias boost circuit is coupled to the base of the first transistor, compensates for changes in temperature of the cascode output stage, and increases a bias current provided to the first transistor responsive to an increase in the temperature of the cascode output stage.

Reducing dynamic error vector magnitude in cascode amplifiers

A radio-frequency (RF) module includes a first transistor having a base, a collector, and an emitter, a radio-frequency output transmit path coupled to the collector of the first transistor at a first end and to a radio-frequency output port at a second end, and an output matching network disposed in the radio-frequency output transmit path, the output matching network including a shunt arm coupled to ground, the shunt arm including a switch that is controllable to modify an impedance of the output matching network.

Cascode power amplifier with switchable output matching network

Apparatus and methods related to multipath bandpass filters with passband notches are provided herein. In certain configurations, a multipath bandpass filter includes multiple filter circuit branches or paths that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a downconverter that downconverts the input signal to generate a downconverted signal, a filter network that generates a filtered signal by filtering the downconverted signal, and an upconverter that upconverts the filtered signal to generate a branch output signal. The filter network includes at least one low pass filter and at least one notch filter to provide a passband with in-band notches. The branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

Multipath bandpass filters with passband notches

Multipath filters are provided herein. In certain configurations, a multipath filter includes multiple filter paths or circuit branches that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a double-in double-switched (DIDS) downconverter that downconverts the input signal with two different clock signal phases to generate a downconverted signal. Each filter circuit branch further includes a filter network that generates a filtered signal by filtering the downconverted signal and an upconverter that upconverts the filtered signal to generate a branch output signal. Additionally, the branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

Multipath filters

Circuits, devices and methods are disclosed, including a phase shifter comprising a first node and a second node, and a first transmission line element having an inductance and a variable capacitance on each side of the inductance, the variable capacitance configured to provide a plurality of capacitance values to yield corresponding phase shift values based on an increment having a magnitude that is less than 90 degrees. In some implementations, the phase shifter further comprises a second transmission line element in series with the first transmission line element, the second transmission line element having an inductance and a variable capacitance on each side of the inductance configured to extend an overall phase shift range provided by the phase shifter.

Circuits, devices and methods related to fine phase shifters

A power amplifier circuit includes a transistor having a first terminal that is configured to receive an input signal, a second terminal electrically coupled to ground, and a third terminal configured to transmit a combined amplified signal. The power amplifier circuit further includes a combining signal input path electrically coupled to the second terminal and configured to receive a combining signal and provide the combining signal to the second terminal of the transistor to generate, at least in part, the combined amplified signal.

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Nepean, Canada

John William Mitchell Rogers