Cisco Technology, Inc.

International Business Machines Corporation

Other

John William Marshall

Darren R Kerr

Kenneth H Potter

Jeffery B Scott

Christopher G Riedle

Kenneth Michael Key

Robert E Jeter, Jr

Scott Nellenbach

Brian R Buchanan

Russell E Schroter

Sagar Borikar

Michael L Wright

Trevor Garner

Barry Scott Burns

Robert Jeter

William Fredenburg

Robert C Olsen

William Robert Lee

Mohammed Ismael Tatar

Atri Indiresan

Matthew Hayden Harper

Carl Thomas Gray

Earl Hardin Booth, Iii

Robert Glen Gerowitz

Michael E Lipman

Raymond Paul Rizzo

James Alexander Markevitch

Stephen Charles Hilla

Robert Leroy King

Herman Levenson

Steven Philip Holmes

Iwan Kartawira

Andrew William Keep

Felix Yuan

Russell Schroter

Aaron Kirk

Donald R Woodward

Vinayak K Parameshwara

Barbara J Marshall

Steve F Kappes

Jeffrey Nelson Shaw

Manish Changela

A method is provided by which a network adapter device receives a packet sent over a network from a peer, the packet including an enqueue timestamp indicating when the packet has been enqueued at the network adapter device. The network adapter device parses a header of the packet to detect whether the header includes bits indicating that the peer device is experiencing congestion, and obtains packet metadata of the packet and the enqueue timestamp of the packet. The network adapter device compares the packet metadata with information in a flow table to identify an entry in the flow table corresponding to a flow to which the packet metadata matches. The network adapter device sets a timer associated with the flow, the timer for use in scheduling transmission of a next packet provided by the host to be sent to the peer.

Automatic rate limiting based on explicit network congestion notification in smart network interface card

In an example, there is disclosed a computing system, including: a processor; a memory; a configuration interface to a logic configuration unit; and a system compiler including: a first block compiler to compile logic for a first logical block in a first language, the first language being a domain-specific language (DSL) and the first logical block being switching logic for a network switch; a second block compiler to compile logic for a second logical block in a second language, the second language being a non-DSL and providing an external accelerator method not supported by the first language; and an interface compiler to define input/output channels for encapsulated data interchange between the first logical block and the second logical block, wherein the encapsulated data interchange is to target a resident instance of the external accelerator method.

Tightly integrated accelerator functions

In one embodiment, an apparatus cascades groups of serialized data streams through devices, and performs operations based on information communicated therein. A received group of serialized data streams is aligned, but not framed, and forwarded to a next device (e.g., a next stage in a linear or tree cascaded formation of devices). Eliminating the framing and subsequent serialization operations performed on the received group of serialized data streams reduces the latency of communications through the cascaded devices, which can be significant when considered in relation to the high-speed communication rates. The received group of serialized data streams is also framed to create a sequence of data frames for processing (e.g., associative memory lookup operations, controlling multiplexing of received downstream serialized data streams, general or other processing) within the device.

Cascaded communication of serialized data streams through devices and their resulting operation

Techniques for processing requests from a processing thread for a shared resource shared among threads on one or more processors include receiving a bundle of requests from a portion of a thread that is executed during a single wake interval on a particular processor. The bundle includes multiple commands for one or more shared resources. The bundle is processed at the shared resource(s) to produce a bundle result. The bundle result is sent to the particular processor. The thread undergoes no more than one wake interval to sleep interval cycle while the bundle commands are processed at the shared resource(s). These techniques allow a lock for shared resource(s) to be obtained, used and released all while the particular thread is sleeping, so that locks are held for shorter times than in conventional approaches. Using these techniques, line rate packet processing is more readily achieved in routers with multiple multi-threaded processors.

Techniques for reducing thread overhead for systems with multiple multi-threaded processors

A versatile and efficient technique for classifying packets in an intermediate node. According to the technique, criteria and rules associated with the packet are applied to one or more classification stages containing content-addressable memories (CAMs). Each stage examines specific criteria associated with the packet, e.g., a packet field, and generates a rule and additional criteria. The additional rule and criteria are provided to the next classification stage. This process continues until a final rule is provided to a final classification stage. At the final classification stage, the final rule is used to generate an identifier, e.g., queue identifier (ID), associated with the classified packet.

Programmable packet classification system using an array of uniform content-addressable memories

In one embodiment, a method includes receiving at a thread scheduler data that indicates a first thread is to execute next a particular instruction path in software to access a particular portion of a shared computational resource. The thread scheduler determines whether a different second thread is exclusively eligible to execute the particular instruction path on any processor of a set of one or more processors to access the particular portion of the shared computational resource. If so, then the thread scheduler prevents the first thread from executing any instruction from the particular instruction path on any processor of the set of one or more processors. This enables several threads of the same software to share a resource without obtaining locks on the resource or holding a lock on a resource while a thread is not running.

Multi-threaded processing using path locks

A technique modifies data transferred from a source to a destination on an intermediate node in a network. According to the technique, a processor of the node issues commands to modify the data. The commands are held in a data structure and not performed on the data until the data is transferred from the source to the destination. As the data is transferred the commands contained in the data structure are performed and the data is modified as directed by the commands.

System and method for modifying data transferred from a source to a destination

A technique for improving utilization of a data link coupled to a network. Scores are generated for one or more data flows that transfer onto the network via the data link. The scores are kept in a 'scorecard' that represents a pool of data flows that are eligible to transfer data onto the data link when the data link becomes idle. Each score represents a rating of a particular data flow's eligibility to transfer data onto the data link when it becomes idle. A check is performed to determine if the data link is idle, and, if so, data associated with the highest scoring data flow are transferred onto the data link.

Supplemental queue sampling technique for packet scheduling

Techniques for distributing data packets over a network link bundle include storing an output data packet in a data flow queue based on a flow identification associated with the output data packet. The flow identification indicates a set of one or more data packets, including the output data packet, which are to be sent in the same sequence as received. State data is also received. The state data indicates a physical status of a first port of multiple active egress ports that are connected to a corresponding bundle of communication links with one particular network device. A particular data flow queue is determined based at least in part on the state data. A next data packet is directed from the particular data flow queue to a second port of the active egress ports. These techniques allow a more efficient use of a network link bundle.

Method and apparatus for dynamic load balancing over a network link bundle

Combined ceiling fan and light

An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.

Inter-chip processor control plane communication

A system and method for enabling a processor to access a memory not directly coupled to the processor. A memory request, including a request identifier field, is issued by a processor to a local memory management unit (MMU). Using the request identifier field, the local MMU determines whether the memory request should be issued by the local memory management unit (MMU) to a local memory, or should be transferred by the local MMU to a remote MMU and issued by the remote MMU to a remote memory, the remote memory associated with a different processor. In this manner, the remote MMU issues certain memory requests on behalf of the local processor and returns any results back to the local processor.

Full access to memory interfaces via remote request

A technique efficiently accesses locks associated with resources in a computer system. A processor accesses (e.g., acquires or releases) a lock by specifying and issuing a request to a resource controller, the request containing attribute and resource location information associated with the lock. In response, the resource controller applies the information contained in the request to an outstanding lock data structure to determine if the request should be blocked, blocked as a pending writer, allowed or an error condition. If the request is blocked, it remains blocked until the outstanding lock blocking the request is released. If the request is allowed, operations associated with the request are performed.

Zero overhead resource locks with attributes

A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.

Processor isolation technique for integrated multi-processor systems

Growing community of inventors

Cary, NC, United States of America

John William Marshall