International Business Machines Corporation

John William Gorrell, Jr

Maximino Aguilar, Jr

James Michael Stafford

Sanjay Gupta

James Arthur Brewer

Norbert M Blam

Yuan-Chang Lo

Michael Edward Criscolo

Roy Moonseuk Kim

A computer system including a processor, a system memory, and a boot code storage device. The system memory is connected to the processor and is suitable for storing processor data and instructions. The boot code storage device includes an image selection indicator for indicating which of multiple boot code images are to be loaded. The computer system further includes means for initiating a boot sequence stored on the boot code storage device. The boot sequence selects from first and second boot images based upon the state of the image selection indicator and loads the selected image into the system memory in response to a boot event. In one embodiment, the image selection indicator is in an initial state until the boot code sequence successfully loads a boot image. The image selection indicator is set to a value indicative of the loaded image when one of the boot images is successfully loaded. The boot code storage sequence attempts, in the preferred embodiment, to load the previously load boot image when the system detects a setting of the image selection indicator indicative of a previously loaded boot image. In the preferred embodiment, the boot code sequence responds to a specified user input sequence by presenting the user with a configuration screen suitable for altering the value of the image selection indicator such that the user may later the boot image that will be loaded during a subsequent execution of the boot sequence. In one embodiment, the first boot image is a BIOS based boot image and the second image is a network based (non-BIOS) boot image. The boot code storage device is preferably a flash memory device.

Method and system for selecting from multiple boot code images to be loaded in a data processing system

A computer network that includes a network server and a network client. The network server includes a storage medium configured with boot code data preferably comprising operating system software for the network client. The network client includes a power status indicator and is configured to query the power status indicator as part of a boot code sequence that is initiated in response to a boot event. The network client is configured to schedule retrieval of boot code data from the network server based upon the power status indicator. Preferably, the power status indicator includes a power fail circuit that indicates whether power to the network client has failed since a previous boot event. In one embodiment, the power fail circuit includes a flip flop arranged such that the output of the flip flop is preset when power is restored to the network client after a power failure. Preferably the clear input of the flip flop is programmably assertable. The power status indicator preferably further includes a power mode indicator that conveys information about the last known power mode of the network client. Preferably, the power mode indicator includes at least one nonvolatile memory bit.

Boot sequence for a network computer including prioritized scheduling of boot code retrieval

A network computer including a motherboard powered by a power supply via a single power supply plane, a clock generator, a processor, a system memory, and a network interface. The network computer is configured to assume a low power state in response to a low power event and further configured to transition from the low power state to a full power state in response to a wake up event. The wake up event may comprise a LAN wake up in the form of a command issued by a server computer coupled to the network computer via a network. In one embodiment, the network computer lacks a disk based storage device, but includes local permanent storage comprising a compact flash card. Preferably, the network computer's clock generator is configured to produce a clock signal for the processor when the network computer is in the full power mode, and further configured to produce no clock signal in the low power mode. In one embodiment, the network computer further includes at least one peripheral device coupled to the processor via a peripheral bus, such as a PCI bus. In this embodiment, the computer is preferably configured to transition each peripheral device on the peripheral bus to a power management mode when the network computer enters low power mode. The wake up event may be a LAN wake up event in which a wake up signal is received via the network interface, or a &ldquo;wake on ring&rdquo; event in which the wake up signal is received via a modem connection to the computer.

Low power mode computer with simplified power supply

A network computer (,) receives instructions from a network manager (,), including a control interrupt instruction, a system management instruction, and a release instruction. A processor (,) associated with the network computer (,) executes the control interrupt instruction first to produce a control interrupt signal. This control interrupt signal causes an operating status controller (,) associated with the network computer (,) to disable local operational status control at the network computer. After local operational status control is disabled at the network computer (,), the processor (,) executes the system management instruction and performs a system management operation at the network computer. Finally, after the system management operation is completed, the processor (,) executes the release instruction to produce a release signal. The release signal causes the operational status controller (,) to enable local operational status control at the network computer (,).

Growing community of inventors

Round Rock, TX, United States of America

John William Gorrell, Jr