Texas Instruments Corporation

John William Fattaruso

Shivaling S Mahant-Shetti

Wai Lee

Khen-Sang Tan

Daramana G Gata

Paul Eric Landman

Marco Corsi

Alan Gatherer

Walter Paul Sjursen

Richard K Hester

Debapriya Sahu

James R Hellums

Venugopal Gopinathan

Benjamin J Sheahan

Michael De Wit

Over the years, ring counter and prescalers have been used in a variety of microelectronic applications, including Phased Locked Loops or PLLs. All of these applications have experienced both decreases in size and increases in speed. As a result, current-mode logic or CML has come into use in some high speed applications, calling for alternative designs for components such as prescalers. Here, a divide-by-three prescaler is described that uses internal states from mater-slave flip-flop pairs and that is well-suited for microelectronics that employ CML.

High speed, symmetrical prescaler

A method and apparatus for providing a low power low voltage differential signaling driver are disclosed. In an example, a low voltage differential signaling driver circuit is described, comprising a first current source to provide current to a first differential pair of PNP transistors, a pair of transresistance amplifiers driven by a corresponding pair of transconductance stages, a second current source to provide current to a second differential pair of PNP transistors, and an output port having a common mode output voltage and a differential output voltage based on a state of the first differential pair of PNP transistors and the second differential pair of PNP transistors.

Low power low voltage differential signaling (LVDS) output drivers

An apparatus for shifting a received signal at a first reference level to an output signal at a second reference level; the received signal including information-indicating signal values; includes: (a) an input locus for receiving the received signal; (b) an output locus for presenting the output signal; (c) a first signal-handling circuit coupled with the input locus and with the output locus and setting the second reference level at the output locus; and (d) a second signal-handling circuit coupled with the input locus and with the first signal-handling circuit; the first signal-handling circuit and the second signal-handling circuit cooperating to convey the information-indicating signal values from the input locus to the output locus.

Apparatus and method for shifting a signal from a first reference level to a second reference level

One embodiment of the present invention includes a pipelined analog-to-digital converter (ADC) comprising a plurality of pipeline stages. At least one of the plurality of pipeline stages comprises a feedback transistor-follower combination interconnected between a positive source voltage and a summation node and configured to set a voltage of the summation node approximately equal to a sample-and-hold voltage associated with a preceding one of the plurality of pipeline stages. The at least one of the plurality of pipeline stages also comprises a current mirror coupled to the feedback transistor-follower combination configured to provide a first current that is approximately equal to a second current that is associated with the feedback transistor-follower combination. The at least one of the plurality of pipeline stages further comprises an output resistor configured to set an output voltage of the respective at least one of the plurality of pipeline stages based on the first current.

Pipelined analog-to-digital converter

A driver apparatus comprising a signal switching circuit coupled for receiving an actuation signal and generating a first and a second control signal in response to the actuation signal; a first control circuit and a second control circuit coupled with the signal switching circuit; the first and second control circuits generating first and second drive control signals in response to the first and second control signals; first and second current generating circuits coupled with the first and second control circuits and coupled with a lower voltage rail; the first and second current generating circuits presenting first and second drive signals at first and second output loci in response to the first and second drive control signals.

Driver apparatus and method of operation thereof

A low distortion compression amplifier comprising an amplifier circuit having an input and an output, wherein an input signal is received at the input and amplified in accordance with a gain to form an output signal at the output. The amplifier circuit further comprises a comparator circuit operable to receive the output signal and generate a first control signal in response thereto. A digital gain control circuit is coupled to the amplifier circuit, and is operable to generate a digital gain control signal based at least in part on the first control signal. The gain control signal is then employed to modulate the gain of the amplifier circuit in a digital fashion. The invention also comprises a method of digitally controlling a gain associated with an amplifier circuit. The method comprises comparing an output signal to a threshold and modulating the gain in a digital fashion, wherein the gain is modulated up in a plurality of rates or down in a plurality of rates in response to the comparison.

Low distortion compression amplifier

A digitally-controlled oscillator (DCO) (), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO () is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (). Each of capacitors () has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger () that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic () that inverts the common node of the capacitors (). The switching time at the input of Schmitt trigger () depends upon the variable load presented by the array of switched capacitors (), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (). A digital phase-locked loop (PLL) clock generator circuit () including a phase detector (), digital loop filter () in combination with the DCO (), and a programmable frequency divider () providing a feedback path from the output of the DCO () to the phase detector (), is also disclosed. The PLL clock generator () may be used in an integrated circuit such as a digital signal processor () or microprocessor, and is particularly well-suited for use in a battery-powered portable electronic system ().

Digitally-controlled oscillator with switched-capacitor frequency selection

A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair Qand Qhaving a tail current source I; a first buffer Qproviding a first input to the differential pair; a second buffer Qproviding a second input to the differential pair; a first current absorbing device Qcoupled to the tail current source Iand having a control node SP capacitively coupled to the first buffer Q; and a second current absorbing device Qcoupled to the tail current source Iand having a control node SM capacitively coupled to the second buffer Q

Differential circuit with current overshoot suppression

A latch device is provided having a latch mode and a transparent mode. In the latch mode, the latch device synchronizes a data signal to a clock signal. In the transparent mode, the data signal drives the output without clock synchronization, such that the clock input signal is unused. The latch device can be employed in an optical driver for optical network laser diodes.

Master-slave latch with transparent mode

The laser driver circuit includes an array of differential pairs and . Each one of the differential pairs is coupled to a corresponding tail current source and . The total modulation current for the laser driver circuit is developed as the sum of the output current from the array of differential pairs and . Each of the tail current sources and generates a subrange of the total range of modulation current. The tail current in a given differential pair will then only vary over a small subrange of the total modulation current range, and the device size in each pair may be optimized to keep the emitter current density near the level that gives optimum bandwidth. This is equivalent to electrically increasing the emitter area of the composite differential pair as the total modulation current is increased, keeping current density approximately constant at its optimal level.

Driver with tail currents in discrete subranges

The opamp with common mode feedback bias includes: a first differential pair M and M having first and second inputs; active load devices M and M coupled to the first differential pair M and M a common mode feedback circuit coupled to the active load devices M and M for controlling the active load devices M and M a second differential pair M and M having a first input coupled to the first input of the first differential pair M and M and a second input coupled to the second input of the first differential pair M and M and current drivers M and M having control nodes coupled to the second differential pair M and M and outputs coupled to the active load devices M and M

Common mode feedback bias for low voltage opamps

An integrated circuit and method of fabrication are disclosed for achieving electrical isolation between a spiral inductor and an underlying silicon substrate using standard semiconductor manufacturing process flow. A spiral conductor with square windings is formed in metal layer ( ) patterned so that straight runs of successive turns ( ) overlie corresponding runs of concentric square rings ( ) formed in underlying metal layer ( ). A unity gain voltage buffer ( ) connects each ring ( ) with a respective overlying turn ( ).

Monolithic inductor with guard rings

A conducting path with a path meander provides a precision voltage-dividing circuit. At each location wherein a voltage level is to be established, the conducting path has an expanded region called a junction region. The centers of all junction regions are equidistant from the centers of neighboring junction regions. Junction regions are positioned at predetermined intervals along the straight portions of the conducting path and at each corner of the path meander. Each junction region has a metal patch extending therefrom. The metal patches are coupled to conducting plugs that, in turn, can be coupled to switching elements of a digital-to-analog converter unit. The junction regions can be altered to increase the precision of the voltage-dividing circuit. Because the junction regions are equidistant from the neighboring junction regions, a cell that includes the switching elements can have a square geometry.

Resistor elements in a resistor divider digital-to-analog converter

A data converter (,). The converter comprises an input (I,-I,) for receiving a digital word. The converter further comprises a string (,) of series connected resistive elements. The string comprises an integer number T of voltage taps (T,&prime;-T,&prime;). The converter further comprises an output (V,) for providing an integer number P of different analog voltage levels in response to the digital word. The integer number P is greater than the integer number T.

Bit interpolation in a resistor string data converter

An analog-to-digital converter (&ldquo;ADC&rdquo;,,) comprising an input (V,) for receiving an input analog voltage. The ADC further comprises a digital-to-analog circuit, comprising a meandering string (,&prime;) of series connected resistive elements (R,&prime;-R,&prime;) having a plurality of voltage taps (T,&prime;-T,&prime;), as well as a number of bit lines (BL,&prime;-BL,&prime;) and a number of word lines (WL,&prime;-WL,&prime;). For a given input analog voltage, the given input analog voltage is closest to a voltage at a selected one of the plurality of taps. In addition, the selected one of the plurality of taps is associated with one of the number of bit lines and one of the number of word lines. Additionally, the ADC further comprises a flash circuit (,CAT,&prime;-CAT,&prime;) coupled to receive the input analog voltage from the input and in response to identify either the one of the number of bit lines or the one of the number of word lines. Lastly, the ADC comprises an output (V,) for providing a digital output value in part in response to the identified one of the number of bit lines or the one of the number of word lines.

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Dallas, TX, United States of America

John William Fattaruso