Seagate Technology Incorporated

John West Dykes

Jon David Trantham

Praveen Viraraghavan

Mohamad H El-Batal

Darshana H Mehta

Ian James Gilbert

Matthew J Totin

Sangita Shreedharan Kalarickal

Tim Rausch

James E Angelo

William D Mosley

Edward Charles Gage

Joel William Hoehn

Mehmet Fatih Erden

Won Choul Yang

Antonia Tsoukatos

Michael Allen Seigler

John Michael Bent

Bruce Douglas Buch

James Gary Wessel

Riyan Alex Mendonsa

Housan Dakroub

Alfredo Sam Chu

James Dillon Kiely

Barmeshwar Vikramaditya

Raul Horacio Andruet

Joshua Ward Christensen

Brian William Karr

Franklin P Martens

Pu-Ling Lu

Jason Paul Zimmerman

James Carl Hatfield, Jr

Richard T Greenlee

Don R Bloyer

Douglas Murphy

Charles Paul Henry

Nan-Husing Yeh

Tony R Blankenhagen

Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

Intelligent management of ferroelectric memory in a data storage device

Described are hard disk drives (HDDs) operable for archival applications and utilizing the same mechanical and electrical design of conventional HDDs. The capacity of a conventional HDD may be extended by up to 25% to 40% or more by employing multiple write and/or read spins before declaring success in write and read processes. The multiple write and/or read spins are designed to address the lower reliability that would otherwise result from high density packing of the data, at the cost of reducing performance. The result is an HDD with lower performance at higher capacity without sacrificing reliability and without altering conventional HDD mechanical or electrical design.

High-density archival storage using conventional hard disk drive architecture

Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

Balancing power, endurance and latency in a ferroelectric memory

A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.

System on chip (SOC) with processor and integrated ferroelectric memory

A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

Read destructive memory wear leveling system

A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).

Non-volatile memory cell with multiple ferroelectric memory elements (FMEs)

Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

Stack register having different ferroelectric memory element constructions

A memory device formed of ferroelectric field effect transistors (FeFETs). The memory device can be used as a front end buffer, such as in a data storage device having a non-volatile memory (NVM). A controller can be configured to transfer user data between the NVM and an external client (host) via the buffer. The FeFETs can be arranged in a two-dimensional (2D) or a three-dimensional (3D) array. A monitor circuit can be used to monitor operation of the FeFETs. An optimization controller can be used to adjust at least one operational parameter associated with the FeFETs responsive to the monitored operation by the monitor circuit. The FeFETs may require a refresh operation after each read operation. A power down sequence can involve a read operation without a subsequent refresh operation to wipe the FeFETs, the read operation jettisoning the data read from the buffer memory.

Front end buffer having ferroelectric field effect transistor (FeFET) based memory

A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

Intelligent cache with read destructive memory cells

A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.

Data storage with multi-level read destructive memory

A base deck for a data storage device includes a body. The body includes a bottom wall and sidewalls that create an internal cavity. The bottom wall includes a textured external surface opposite the internal cavity. The base deck can be coupled to a cover to seal the internal cavity.

Methods and devices for alleviating thermal boil off in immersion-cooled electronic devices

A data storage device includes a base deck coupled to a top cover. The data storage device includes a printed circuit board coupled to and spaced from the base deck. The data storage device also includes a thermal interface material positioned between the printed circuit board and the base deck and comprising a porous material.

Thermal interface materials for immersion cooled data storage devices

A first heat-assisted magnetic recording (HAMR) writer writes to a surface of a magnetic disk using during an initial time period. A second HAMR writer is configured to write to the surface but not during the initial time period. The initial time period extends from a first time when the disk drive is first used to a second time when a near-field transducer of the first HAMR writer reaches a first wear threshold. During a subsequent time period after the initial time period, to the surface of the disk is written to using the second HAMR writer and not the first HAMR writer.

Heat-assisted magnetic recording device with multiple writers that write to the same disk surface at different time periods

In a data storage device where a data writer is predicted to fail, cold data can be identified and subsequently moved to a data storage medium corresponding to the failing data writer. The data writer may be positioned proximal the data storage medium where data is stored. A controller can predict the failure in the data writer and transition all the data in the data storage medium to a read only status.

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Eden Prairie, MN, United States of America

John West Dykes