Rambus Inc.

Nvidia Corporation

Quantum Corporation

Lattice Semiconductor Corporation

Maxtor Corporation

John Welsford Brooks

Frederick Abbott Ware

Ely K Tsern

Brian S Leibowitz

Wayne Frederick Ellis

Akash Bansal

Kishore Ven Kasamsetty

Thomas Vogelsang

Richard E Perego

Benedict C Lau

Nirmal Raj Saxena

Bret G Stott

Peter C Mills

Chanh Vi Tran

Michael Brendan Sullivan

Eugene C Ho

Philip Yeung

Knut Stener Grimsrud

Farshid Aryanfar

Trung T Nguyen

Hung C Nguyen

Anthony Leigh Priborsky

Richard J Blackborow

Jeffery H Appelbaum

Tim R Glassburn

James P McGrath

Hang Nguyen

Parminder K Gill

Faheem Dani

Garrick Yeung

Jeffrey Herbert Appelbaum

Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Techniques for storing data to enhance recovery and detection of data corruption errors

Various embodiments include an on-die error correction code (ECC) system that preserves rectangular symbols of arbitrary size and shape, where the dimensions of the symbol are powers of two. Further, the on-die ECC system preserves symbols that include multiple rectangles of arbitrary size and shape, where the dimensions of each rectangle are powers of two, and where the vertical and horizontal offset between consecutive rectangles are also powers of two. If the on-die ECC system miscorrects a memory bit, then the miscorrection is constrained or restricted to the same symbol that includes the other error bits. Therefore, all error bits, including the miscorrected bit, are in the same symbol. As a result, a user ECC system, such as a symbol-based ECC system, can correct and detect any number of errors within a single symbol, even when the on-die ECC system miscorrects a memory bit.

Techniques for generating symbol-preserving error correction codes

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such 'microthreading' provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

Memory component with multiple command/address sampling modes

Memory control component with dynamic command/address signaling rate

Memory control component with inter-rank skew tolerance

The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an 'opportunity' to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

Memory refresh method and devices

High capacity memory systems with inter-rank skew tolerance

A method of tracking a second electronic device with respect to a first electronic device is disclosed. The method includes transmitting a first waveform of a first frequency along a first fixed path associated with the first device. A second waveform having a frequency based on the first frequency is wirelessly transmitted from the first device to the second device along a first wireless path. The second waveform is wirelessly transmitted from the second device to the first device along a second wireless path. The first and second waveforms are received at the phase comparator circuit. A first phase relationship of the received first waveform is then compared to a second phase relationship of the received re-transmitted waveform. A coordinate of the second device is determined with respect to a reference coordinate based on the comparing.

Low-cost tracking system

An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

Self-test method for interface circuit

Interface test circuit

A method and system of providing access to a shared memory interconnected to a first controller and a second controller via a bus, the bus having control signals associated therewith for data transfer control and communication between the first and the second controllers. The second controller transmits an access request to the first controller for control of the bus to access the memory. The first controller selectively grants the access request and transmits an acknowledge to the second controller; and upon receiving the acknowledge, the second controller accesses the memory for data transfer. The first controller has a first priority for accessing the memory, and the second controller has a second priority for accessing the memory, the second priority being lower than the first priority such that upon request the first controller selectively grants control of the bus to the second controller for memory access, otherwise the first controller maintains control of the bus for memory access. In one embodiment, the second controller transmits an access request to the first controller for control of the bus to access the memory; and in response, the first controller selectively grants the access request and transmits an acknowledge to the second controller. Each of the controllers relinquishes control of the bus by placing the bus in tristate, wherein the relinquishing controller stops driving the bus.

Control system, storage device and method for controlling access to a shared memory using a bus control or handshaking protocol

A method for reducing radio frequency interference from a high frequency serial bus by scrambling data signals and reducing the repetition of control signals. Beginning and ending control signals are provided with meaningless signals provided therebetween.

Method for reducing radio frequency emissions on high-speed serial buses

A synchronous DMA burst transfer method is provided for transferring data between a host device and a peripheral drive device connected by an ATA bus. The method provides synchronous data transfer capability in an asynchronous system by having one device in charge of both a strobe signal and a data signal. When a host read or write command is delivered to the peripheral drive device, the peripheral device decides when to start the synchronous DMA burst. For a read command, the peripheral device requests the synchronous DMA burst then drives a data word onto the ATA bus after the host acknowledges that it is ready to begin the burst. After allowing time for the data signal to settle, the peripheral device toggles a strobe signal from a high state to a low state. The host sees the edge of the strobe signal at which time the host latches the data word on the bus. Additional data words can be driven on the bus and the strobe signal can be retoggled to latch the additional data words into the host. After all data words have been transferred, the strobe signal is returned to a high state so that it is ready to be used for another host command. By having the device which is sending the data in charge of both the strobe signal and the data signal, the method reduces timing delays and provides a data transfer rate up to 33 MBytes/sec. The method is easily implemented in existing systems and is backward compatible with existing transfer protocols.

Synchronous DMA burst transfer protocol having the peripheral device

Growing community of inventors

San Jose, CA, United States of America

John Welsford Brooks