Motorola Corporation

Intel Corporation

Fujitsu Semiconductor Limited

John Wayne Simmons

Kristopher Kevin Kaufman

Walter H Kehler

Virgilio A Fernandez

Barry W Herold

Charles R Ruelke

James G Mittel

Chin Pan Wong

Raymond Louis Barrett

Grazyna A Pajunen

John J Parkes, Jr

Norman T Rollins

Manbir Nag

John D Wetters

Nihal J Godambe

Kai Zhong

Keith Edward Jackoski

James C Goatley

Mansour Ghomeshi

Steve Carsello

Art Ahrens

Gerald Paul Schwieterman

In accordance with some embodiments of the present disclosure, an oscillator circuit comprises, a first pad associated with a first terminal of an oscillator and a second pad associated with a second terminal of the oscillator. The oscillator is configured to generate an oscillating signal and communicate the oscillating signal from the second terminal to a clock distributor coupled to the second pad. The oscillator circuit further comprises an oscillator gain element comprising an output node coupled to the first pad and an input node coupled to the second pad. The oscillator circuit also comprises a digital-to-analog converter (DAC) coupled to the first pad. The oscillator circuit additionally comprises a switching circuit coupled to the gain element. The switching circuit is configured to enable the gain element when the oscillator comprises a resonator and disable the gain element when the oscillator comprises a voltage controlled oscillating module.

System and method for supporting different types of oscillator circuits

In accordance with some embodiments of the present disclosure, an oscillator may include a crystal resonator and a squaring circuit coupled to the crystal resonator and configured to convert a sinusoidal signal produced by the crystal resonator to a square-wave signal, the squaring circuit comprising a bias circuit configured to transmit a selected bias voltage for the squaring circuit, the selected bias voltage selected from a plurality of potential bias voltages. In accordance with this and other embodiments of the present disclosure, an oscillator may include a crystal resonator, an inverter coupled in parallel with the crystal resonator, and a programmable voltage regulator coupled to the inverter. The programmable voltage regulator may be configured to supply a first supply voltage to the inverter during a startup duration of the oscillator, and supply a second supply voltage to the inverter after the startup duration, wherein the second supply voltage is lesser than the first supply voltage.

System and method for amplitude contorl of a crystal oscillator

System and method for duty cycle control of a crystal oscillator

Systems and methods for reducing voltage undershoot and overshoot of a voltage regulator are disclosed. In one embodiment of the present disclosure, an undershoot/overshoot regulation circuit comprises a control node having a control voltage. The regulation circuit also comprises a control circuit configured to increase the control voltage in response to a load being applied to an output node of a voltage regulator and decrease the control voltage in response to the load being removed from the output node. The regulation circuit also comprises a control capacitor including a first terminal coupled to the control node and a second terminal coupled to a gate node of the voltage regulator. The control capacitor is configured to increase a gate voltage at the gate node in response to the increase of the control voltage, and decrease the gate voltage in response to the decrease of the control voltage.

Capless regulator overshoot and undershoot regulation circuit

An oscillator may include a crystal resonator, an inverter coupled in parallel with the crystal resonator, a first switched capacitor coupled to a first terminal of the crystal resonator, a second switched capacitor coupled to a second terminal of the crystal resonator, a control module configured to output a periodic dithering signal, the periodic dithering signal having a first pulse width based on a desired frequency of oscillation for the oscillator, and a delay module configured to communicate a first periodic enable signal to enable the first switched capacitor and a second periodic enable signal to enable the second switched capacitor. At least one of the first periodic enable signal and the second periodic enable signal may have a second pulse width greater than the first pulse width. The second periodic enable signal may be phase delayed relative to the first periodic enable signal by a non-zero delay.

System and method for crystal oscillator frequency tuning

A power management system has a primary power source () and a secondary power source () generated from the primary power source () with a power output selector () coupled to each for selecting power for a regulated power output (). First, during initialization and at any other time during operation, when the primary power source () exceeds the secondary power source (), the primary power source () is used as a power supply for the regulated power output (). Second, at any time after initialization that the primary power source () exceeds the regulated power output (), the primary power source () is used as the power supply for the regulated power output (). Third, at any time after initialization that the secondary power source () exceeds the primary power source () and the primary power source () is less than the regulated power output (), the secondary power source () is used as the power supply for the regulated power output ().

Dual mode power management system

A communication module includes a variable gain amplifier, a mixer stage responsive to the variable gain amplifier, a post-mixer amplifier stage responsive to the mixer stage, and an off-channel signal detector responsive to the post-mixer amplifier stage. The post-mixer amplifier stage is to produce a first differential signal and a second differential signal. The off-channel signal detector has a first input to receive the first differential signal and has a second input to receive the second differential signal. The off-channel signal detector includes a programmable hysteresis comparator module, and the off-channel signal detector has an output to produce an output signal that indicates whether an off-channel signal condition is detected.

Off-channel signal detector with programmable hysteresis

A ring inhibiting charging and discharging circuit (,) for use with an amplification circuit (,) that drives a load (,) is responsive to an input (,) and is capable of generating an output (,) corresponding to the input (,). The ring inhibiting charging and discharging circuit (,) includes a charge element (,) that is responsive to the output (,) from the amplification circuit (,). The charge element (,) is capable of charging the load when the input voltage is greater than a preselected multiple of the output voltage. A discharge circuit (,) is responsive to the output (,) from the amplification circuit (,) and includes a feedback circuit (,) and a staging circuit (,). The feedback circuit (,) asserts a difference signal when the output voltage is less than the preselected multiple of the input voltage. The staging circuit (,) is responsive to difference signal and gradually reduces the rate at which the load (,) is discharged over a preselected period of time once the difference signal indicates that the output voltage is within a preselected range of the input voltage.

High capacitance drive fast slewing amplifier

An oscillator circuit (10) having an optimized start up time includes an inverting amplifier (12) coupled in parallel to a crystal (14), a first bank of capacitors (16) coupled to the crystal, and a second bank of capacitors (20) switchably coupled (18) in parallel to the frequency resonant network, wherein the second bank of capacitors has a higher capacitance load than the first bank of capacitors. The oscillator circuit may also include a processor (62) for controlling when the second bank of capacitors gets switched and coupled to the crystal.

Method and apparatus for optimizing an oscillator start up time

A low power, fast starting oscillator (10) of the Colpitts type includes an amplifier (12) that provides voltage gain and feeds a source follower circuit (14) that provides a desirable output impedance. A crystal (16) is coupled from an output of the source follower circuit (14) back to the amplifier's input (32). The voltage gain of the amplifier (12) and the output impedance of the source follower circuit (14) are independently selectable to provide an optimum transconductance for the oscillator (10) to start quickly. When oscillations reach a threshold value, the transconductance may be reduced to save power.

Fast starting oscillator

A method of calibrating a radio receiver (100) which has a desired IF center frequency (fo) includes generating and applying to the receiver's demodulator (126) a plurality of reference signals. The demodulated reference signals are used to generate, for the demodulator, a transfer function that is predictive of amplitude versus frequency characteristics of signals to be demodulated by the demodulator (126). The transfer function (202) is used to determine a frequency offset between a received signal's intermediate frequency and the desired frequency fo. The determined frequency offset is used to adjust the IF frequency of the received signal towards the desired frequency fo. The adjustment process preferably continues until the frequency offset is below a desired threshold. A receiver using the disclosed method is also described.

Radio receiver and method of calibrating same

A squelch circuit (118) is provided having a squelch hysteresis window for preventing squelch chatter in a communication device (100). The communication device (100) includes a plurality of squelch states. The squelch circuit (118) comprises a first means (206) for sensing when the communication device (100) is in a first squelch state. The squelch circuit (118) also includes a second means (116) which is responsive to the first means (206) for varying the squelch hysteresis window to prevent squelch chatter.

Method and apparatus for prevention of squelch chatter

A squelch circuit (200) having an input is provided including a programmable high pass filter (206) for filtering the input signal to produce a filtered signal. The filtered signal is rectified via a differential rectifier (201) to produce a rectified signal. The squelch circuit (200) also includes a threshold comparator (323) coupled to the differential rectifier (201) for sensing when the rectified signal exceeds a squelch threshold.

Comparator switched squelch rectifier

A communication device (100) having a receiver (106) and an audio output device (116) is provided. The communication device (100) includes a digital signal processor DSP (110) for measuring the level of signal energy in a first segment of the frequency spectrum of the received signal to dynamically establish a squelch threshold. The DSP (110) is also used to measure the level of signal energy in a second segment of the frequency spectrum of the received signal. The communication device (100) also includes audio gates (114). The audio gates (114) provides for the unmuting of the audio output device (116) when the signal energy contained in the second segment of the frequency spectrum of the received signal is below the squelch threshold.

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Tamarac, FL, United States of America

John Wayne Simmons