International Business Machines Corporation

John Wayne Hartfiel

Robert Christopher Dixon

Tung Nguyen Pham

Hien Le

Neil A Panchal

Hein Minh Le

Adron Marcus Washington

The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.

Multi-chip digital system having a plurality of controllers with self-identifying signal

The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. The processor is coupled to the controller and configured to generate self-identify control signals and to transmit the self-identify control signals to the controller.

Multi-chip digital system having a plurality of controllers with input and output pins wherein self-identification signal are received and transmitted

An apparatus, a method, and a computer program product are provided for identifying signals in analogue electrical systems. The ID select signals that control the timing of this signal identification circuit comprise sequential numbers that count up and identify a corresponding signal. The signals to be identified are located on a group of input/output (I/O) pins. One multiplexer (first) selects a specific I/O pin in response to the ID select signals. An isolated voltage source is connected to this multiplexer and provides the selected signal to another multiplexer (second). The second multiplexer switches from this isolated voltage source to ground potential in response to the ID select signals. The isolated voltage source floats at the DC level of the selected I/O driver pin. Therefore, by connecting to the selected signal's I/O pin and the output of the second multiplexer, the selected signal can be identified and then probed.

Signal identification method and apparatus for analogue electrical systems

An apparatus, a method, and a computer program product are provided for producing a synchronous divider reset signal. A notorious concern with multiple non-integer frequency ratio synchronous source clocks has been the time of edge alignment between the respective clocks. To address this concern, a number of latches can be utilized in order to detect alignment of the edges of these clocks. Specifically, the latches are employed to assist in the production of a synchronous divider reset signal for downstream dividers that are utilized in many microprocessors today. Hence, all of the downstream dividers can be properly synchronized to alleviate any errors that can occur between respective macros of a microprocessor chip resulting from misalignment of clock edges.

Method and apparatus for ensuring synchronization of clocks in a multiple clock system

An interface cable which allows access to an operational Peripheral Component Interconnect (PCI) bus compatible circuit board is disclosed. A flat flexible cable (30,72) secures a plurality of connectors (50,32,36,38) at substantially equal intervals. The connectors on the flat cable are adapted to receive a connection (62,63,64,66,68) on a first edge of the PCI compatible circuit board (82,90). When the PCI compatible circuit board is plugged into the flat flexible cable, a second edge of the PCI compatible circuit board which is opposite the first edge is free to move laterally, away from neighboring circuit boards in response to a flexing of the flat flexible cable. Open space is created adjacent to the PCI compatible circuit board allowing sufficient access to surfaces of the functioning PCI compatible circuit board for testing purpose.

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Austin, TX, United States of America

John Wayne Hartfiel