Allegro Microsystems, LLC

John Waranowski

Aaron Cook

Virag V Chaware

Kenneth Snowdon

A sensor integrated circuit includes a disturb immune memory configured to store data and a digital processor coupled to the disturb immune memory and including a main register. The digital processor is configured to perform one of a fast reset or slow reset of the main register according to a level of a supply voltage to the integrated circuit. The fast reset includes resetting the main register according to the data stored in the disturb immune memory and the slow reset includes resetting the main register according to a default state.

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Weare, NH, United States of America

John Waranowski