Intel Corporation

John Wai Fu

Dean A Mulla

Nhon Toai Quach

Sunny C Huang

Jeen Miin

Stefan Rusu

Gregory Scott Mathews

Simon M Tam

Len J Schultz

Jim Hays

A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol different from the first symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.

Combined tag and data ECC for enhanced soft error recovery from cache tag errors

Processor implementation-specific instructions save a processor state in a system memory and attempt to correct the error. Control is then transferred to processor-independent instructions. Control is returned to the processor implementation-specific instructions which then return to an interrupted context of the processor by restoring the processor state.

Method of correcting a machine check error

A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.

A method and apparatus for storing, locking, and unlocking data in a memory array. The memory array includes a first line to store a first type of data while the first line is unlocked during a first period of time and to store a second type of data while the first line is locked during a subsequent second period of time. The memory array further includes a second line to store the second type of data while the second line is locked during the first period of time and to store the first type of data while the second line is unlocked during the second period of time.

Method and apparatus for storing data in a memory array

The invention comprises, in one aspect, a content addressable memory array having a plurality of memory locations to store tag words. The content addressable memory array includes a parity encoder and a parity comparator. The parity encoder has a first input terminal to receive an input data signal and a first output terminal to deliver a signal representative of the parity of the input data signal. The parity comparator has a second input terminal, a third input terminal connected to the first output terminal, and a plurality of memory cells to store original parities of the tag words. The parity comparator compares the original parity of a first tag word to the parity of the input data signal in response to a receiving a match signal. The content addressable memory array includes a fourth input terminal to receive the input data signal, and a second output terminal to send the match signal in response to one of the tag words matching the input data signal. The second output terminal connects to the second input terminal.

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Saratoga, CA, United States of America

John Wai Fu