Intel Corporation

John Wai Cheong Fu

Dean A Mulla

Gregory Scott Mathews

Stuart E Sailer

Jeng-Jye Shaw

John H Crawford

Gautam B Doshi

A method is provided for requesting data from a memory. The method includes issuing a plurality of data requests to a data request port for the memory. The plurality of data requests includes at least two ordered data requests. The method includes determining if an earlier one of the ordered data requests corresponds to a miss in the memory, and converting a later one of the ordered data requests to a prefetch in response to the earlier one of the ordered data requests corresponding to a miss in the memory. An apparatus includes a memory having at least one pipelined port for receiving data requests. The port is adapted to determine whether an earlier ordered one of the data requests corresponds to a miss in the memory. The port converts a later ordered one of the data requests to a prefetch in response to determining that the earlier ordered one of the data requests corresponds to a miss in the memory.

Processing ordered data requests to a memory

A method is provided for managing temporal and non-temporal data in the same cache structure. The temporal or non-temporal character of data targeted by a cache access is determined, and a cache entry for the data is identified. When the targeted data is temporal, a replacement priority indicator associated with the identified cache entry is updated to reflect the access. When the targeted data is non temporal, the replacement priority indicator associated with the identified cache entry is preserved. The method may also be implemented by employing a first algorithm to update the replacement priority indicator for temporal data and a second, different algorithm to update the replacement priority indicator for non-temporal data.

Method and apparatus for managing temporal and non-temporal data in a single cache structure

A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The cache design allows two cache requests to be processed simultaneously (dual-ported) and concurrent cache requests to be in-flight (pipelined). The design of the cache allocates a first clock cycle to cache tag and data access and a second cycle is allocated to data manipulation. The memory array circuit design is simplified because the circuits are synchronized to the main processor clock and do not need to use self-timed circuits. The overall logic control scheme is simplified because distinct cycles are allocated to the cache functions.

High performance fully dual-ported, pipelined cache design

A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB memory having a plurality of entries and a second-level TLB memory operatively coupled to the first level TLB memory. The second-level TLB memory also has a plurality of entries. Entries are placed in the TLB and TLB structure as a result of software controlled translation register operations and hardware controlled translation cache operations. Logic controlling TLB treats both operations the same way and uses a hardware replacement algorithm to determine the entry index. Logic controlling TLB uses a hardware replacement algorithm to determine the entry index for translation cache entries, and use an index provided within the insertion instruction to determine the entry index for translation register operations.

Hierarchical fully-associative-translation lookaside buffer structure

A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The on-chip cache memory has two levels. The first level is optimized for low latency and the second level is optimized for capacity. Both levels of cache are pipelined and can support simultaneous dual port accesses. A queuing structure is provided between the first and second level of cache which is used to decouple the faster first level cache from the slower second level cache. The queuing structure is also dual ported. Both levels of cache support non-blocking behavior. When there is a cache miss at one level of cache, both caches can continue to process other cache hits and misses. The first level cache is optimized for integer data. The second level cache can store any data type including floating point. The novel two-level cache system of the present invention provides high performance which emphasizes throughput.

Dual-ported, pipelined, two level cache system

A method and apparatus for performing cache accesses. A comparator is coupled to a cache and a lookup parity bit line to perform error detection.

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Saratoga, CA, United States of America

John Wai Cheong Fu