Ncr Corporation

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Symbios Logic Inc.

John W Stewart

Rodney A Dekoning

Dennis E Gates

Thomas L Langford, Ii

Curtis W Rink

Ronald L Bruckner

Philip W Bullinger

Darrell W Woelk

Marvin R DeForest

A high performance scaleable hardware architecture for a disk array storage subsystem which supports RAID modes 0, 3, 4 and 5. The architecture features a high bandwidth parity calculation engine, a buffered PCI interface operating at the full speed of the PCI bus, and a dedicated local memory. The dedicated local memory is dual ported so that PCI and parity operations may operate concurrently. The architecture of the disk array controller allows parity calculations and memory block moves to occur without interfering with the controller processor or its associated memory, freeing the controller processor to manage array task control. The array controller configuration allows simultaneous operation of data block moves between storage I/O devices and local memory; data block moves between host SCSI connections and local memory; parity calculations; and normal CPU memory fetches, queued operations for block moves and queued operations for parity tasks.

Disk array storage system architecture for parity operations

A first inverter circuit is coupled between a first voltage source and a reference potential by a plurality of cascaded transistors. Each of the cascaded transistors has a control gate which may be selected to bring the resistance of the transistor into circuit with the inverter circuit to control the charging rate of a distributed capacitance. An output circuit coupled to the first inverter circuit provides the distributed capacitance and an inverted buffered output. The output circuit also includes an output which may be connected to another circuit of the present invention to form a cascaded delay circuit and to receive a reset signal for resetting the cascaded delay circuit.

Digitally controlled delay circuit

For LSI/VLSI integrated circuits which inherently have an address decoder and a data bus, a scan testing method and apparatus is presented which does not require additional pin connections to be dedicated for scan test implementation. Counter to the Joint Test Action Group approach, the present invention uses additional registers, multiplexers, and decoders in conjunction with the existing buses to provide test access to otherwise embedded layers of logic circuitry, without the addition of a single pin connection to a integrated circuit chip package. Further, since this test method and apparatus uses the data bus and registers just as the rest of the chip, slow and complex d.c. level shifting equipment is not required.

Bus executed scan testing method and apparatus

A digitally controlled timing circuit for providing an output pulse signal precisely delayed with respect to an input signal irrespective of the time of occurrence of a system clock, but which uses the precision of the system clock to self-correct any inaccuracy in the delay includes a plurality of delay elements, the delay period of a respective one of which is adjustable, coupled between an input terminal, to which an input terminal is applied, and an output terminal, from which a delayed output signal is to be derived. Coupled to the input terminal and the plurality of delay elements is a toggled flip-flop which, with the delay elements, during a calibrate mode, forms an adjustable oscillator and generates a sequence of signals the lapse of time between successive ones of which is established by delays imparted by selected ones of the delay elements. The delays imparted by selected ones of the delay elements. The output of the flip-flop is coupled to a shift register/counter which is used to measure the length of time required for the flip-flop to generate a prescribed number of signals after its receipt of an input signal. Upon counting a prescribed number of signals generated by the flip-flop the shift register/counter delivers an output signal to a comparator, which compares the length of time measured by the shift register/counter with a reference length of time. Depending upon the comparison, an up/down counter is incremented or decremented. Decoded contents of the counter are used to adjust the delay elements.

Self-correcting digitally controlled timing circuit

An associative memory system including a plurality of associative data controllers (ADCs) which operate in parallel upon a mass storage including a storage array for each ADC. A primitive function processor (PFP) couples the ADCs to a control unit which provides user access to the system. Hardware instructions are issued by the PFP to the ADCs to enable them to operate in parallel. The ADCs have circuits for performing simultaneous read/write operations with their related storage arrays, and for performing tagging operations, minimum/maximum operations, and logical operations.

Associative memory system

A circuit provides means for driving a load under control of a plurality of signals including a drive timing signal which is given a maximum permissible duration by the circuit to prevent damage to the load, an operating signal, and an inhibit signal which prevents operation in case of excessively low power supply voltage. A power supply of opposite polarity is connected to the load so that the load rapidly dissipates its energy into said power supply at the time of turn-off of the drive circuit.

Drive circuit

A driver circuit for limiting the magnitude of current flowing through a solenoid wherein the level of the current flowing through the solenoid is sensed and fed back to a driving switch. A level of current above a set level cuts off the drive voltage allowing the current in the solenoid to decay. A timing means fixes the time that the driving switch is off. During off times a conserving voltage is applied to the solenoid to prevent the rapid decay of the solenoid current.

Solenoid driver circuit

A circuit for applying a driving voltage to an inductive load for a period of time sufficient to increase the current in the load to a maximum desired level, and for disconnecting the driving voltage for fixed intervals between each application so as to maintain the level of current flow through the inductive load below the maximum desired level so as to permit the application of a high drive voltage without causing excessive heating in the inductor.

A circuit provides means for controlling the energy derived from operation of a load by delivering a timed output pulse which is a function of the applied circuit voltage. Operation of a variable charging means, coupled across the applied circuit voltage, is initiated by application of an input signal to the circuit and charges at a rate dependent upon the applied circuit voltage. A differential amplifier, responsive to the condition of the charging means, controls a driver which operates a latch to determine the duration of the output pulse.

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Wichita, KS, United States of America

John W Stewart