Motorola Corporation

John W Steele

Edouard D De Fresart

N David Theodore

Jay Paul John

James Albert Kirchgessner

Richard W Mauntel

Jenny M Ford

Michael H Kaneshiro

Vida Ilderem Burger

Edouard De Fr&eacute;sart

David L Stolfa

Zhirong Tang

Curtis Lee Burt

Ik-Sung Lim

David Theodore

Donald Y Lie

Phillip W Dahl

Cliff Stein

T C Smith

A method of manufacturing a semiconductor component includes providing a substrate ( ) having a first doping concentration and growing an epitaxial layer ( ) over the substrate. The epitaxial layer has a second doping concentration lower than the first doping concentration, and the epitaxial layer has at least two effective, as-grown thicknesses. The resulting composite substrate is suitable for an integrated circuit having both high and low voltage portions.

Method of manufacturing a semiconductor component and semiconductor component thereof

A method of manufacturing a heterojunction BiCMOS IC. ( ) includes forming a gate electrode ( ), forming a protective layer ( ) over the gate electrode, forming a semiconductor layer ( ) over the protective layer, depositing an electrically insulative layer ( ) over the semiconductor layer, using a mask layer ( ) to define a doped region ( ) in the semiconductor layer and to define a hole ( ) in the electrically insulative layer, forming an electrically conductive layer ( ) over the electrically insulative layer, using another mask layer ( ) to define an emitter region ( ) in the electrically conductive layer and to define an intrinsic base region ( ) and a portion of an extrinsic base region ( ) in the electrically conductive layer, and using yet another mask layer ( ) to define another portion of the extrinsic base region in the electrically conductive layer.

Method of manufacturing a heterojunction BiCMOS integrated circuit

A heterojunction bipolar transistor (HBT) (30) is formed to have a germanium composition profile (46) in a base region (32) that improves the tolerance of the HBT device (30) to manufacturing variations and reduces the sensitivity to emitter/base biases. A first region (40) of essentially constant germanium composition is formed at the interface of an emitter region (34) and the base region (32). The germanium composition profile (46) also has a second region (41) in which the germanium composition is increased linearly to provide an acceleration field by reducing the band gap in this second region (41). The acceleration field reduces the transit time of carriers and increases the frequency response of the HBT device (30).

Heterojunction semiconductor device and method of manufacture

A method for doping a strained heterojunction semiconductor device includes heating a substrate (16) having a strained mono-crystalline semiconductor region (22) to a temperature above room temperature. While the substrate (16) is heated, dopants are ion implanted into the strained mono-crystalline semiconductor region (22) to minimize implant related damage. Thereafter the substrate (16) is heated under non-steady state conditions for a time sufficient to activate the implanted dopant and anneal implant related damage while minimizing relaxation of the strained heterojunction.

Method for doping strained heterojunction semiconductor devices and

A method for selectively forming semiconductor regions (28) is provided, by exposing a patterned substrate (21) having exposed regions of semiconductor material (26,27) and exposed regions of oxide (24) to a first temperature and a semiconductor source-gas and hydrogen in an atmosphere substantially absent halogens, a blanket semiconductor layer (28,29) forms over the exposed regions of semiconductor material (26,27) and oxide (24). By further exposing the patterned substrate (21) to a second temperature higher than the first temperature in a hydrogen atmosphere, polycrystalline semiconductor material (29) formed over the exposed oxide regions (24) is selectively removed leaving that portion of the blanket semiconductor layer (28) over the exposed regions of semiconductor material (26,27). The method is suitable for forming isolated regions of semiconductor material for fabricating semiconductor devices and is not load dependent.

Method for selectively forming semiconductor regions

One preferred method for making a semiconductor structure includes altering the direction, and optionally the position, of a polycrystalline grain boundary (38) in a base layer (17,21) of an epitaxial base bipolar transistor (10). Altering the grain boundary (38) may be accomplished by annealing the semiconductor structure after the layer, which later forms the lower portion of the base (17), has been deposited. Altering the grain boundary (38) has a significant effect in reducing base resistance (R.sub.bx1, R.sub.bx2). Reduced base resistance (R.sub.bx1, R.sub.bx2) dramatically improves device performance.

Method for reducing base resistance in epitaxial-based bipolar transistor

A non-strained epitaxial layer is formed to have a small transition width and a low amount or no amount of oxygen incorporated therein. During the formation of non-strained epitaxial layer, a germanium source gas is introduced. Germanium reacts with water and/or oxygen to form GeO, which sublimates from the surface of the non-strained epitaxial layer, instead of oxygen being incorporated into the lattice. Thus, a low temperature epitaxial process can be used to obtain the small transition width without having oxygen incorporated into the non-strained epitaxial layer.

Low temperature silicon epitaxy with germanium doping

An epitaxial reactor (10) includes a bell jar (11) wherein epitaxial depositions are performed. During an epitaxial deposition cycle, the temperature of the bell jar (11) is monitored by an infrared detector (22). After the temperature reaches a predetermined value, initiation of further epitaxial deposition cycles is inhibited. The control method extends the useful lifetime of heating lamps (12) and bell jar seals thereby reducing the cost of semiconductor wafers (16).

Silicon epitaxial reactor and control method

A bipolar transistor (10) is formed by using low temperature epitaxial deposition in order to form a base layer (14) of the transistor (10). A dielectric (16, 17, 18) is applied to the base layer (14) and an emitter opening (21) having sloping sidewalls is formed in the dielectric (16, 17, 18). Low temperature epitaxial deposition is also used for forming an emitter (24) within the emitter opening (21). The emitter opening (21) forms sloping sidewalls on the emitter (24) thereby forming an emitter overhang that overlies the base layer (14). The width (26) of the emitter overhang determines an extrinsic base width of the transistor (10).

Method of forming a bipolar transistor having an emitter overhang

A method of forming a silicon-germanium epitaxial layer using dichlorosilane as a silicon source gas. A semiconductor seed layer (15) is formed on a portion of a semiconductor layer (12) and on a portion of a layer of dielectric material (13). The semiconductor seed layer (15) provides nucleation sites for a Si-Ge epitaxial alloy layer (16). The epitaxial film (16) is formed on the semiconductor seed layer (15). Both the semiconductor seed layer (15) and the Si-Ge epitaxial film (16) are formed at a system growth pressure between approximately 25 and 760 millimeters of mercury and a temperature below approximately 900.degree. C. The semiconductor seed layer (15) and the Si-Ge epitaxial film (16) permit fabrication of a heterostructure semiconductor integrated circuit (10), thereby allowing the exploitation of band-gap engineering techniques.

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Chandler, AZ, United States of America

John W Steele