Rockwell Collins, Inc.

John W Roltgen

Mark A Kovalan

Mark Clifford Singer

James J Corcoran

Samir S Hemaidan

Eric J Danielson

Douglas Robert Johnson

John P Perich

Thomas M Scanlon

James E Sisson

John L Persick

Juan M Segal

Samuel E Ferdon

Andrew R Markofski

Douglas L Bader

Zafar S Ahmad

Brandon J Burnett

Dale E McPherson

Corydon J Carlson

Cleveland C Gilbert

Shawn M Stanger

Autonomous systems increase the robustness and safety of current aircraft and to support simplified vehicle, reduced crew, and single pilot operations. The autonomous systems aid air crews in their handling of non-normal, high workload, aircraft upset scenarios. The upset scenarios include the recovery from attitudes outside of the normal operating envelope that even the most robust automatic flight control systems currently in service today do not support.

Multi-axis upset recovery system

A system and method are provided for controlling aircraft flight control surfaces. The system may include at least three pilot sensor channels, each pilot sensor channel including a set of pilot sensor data. The system may also include at least three aircraft sensor channels, each aircraft sensor channel including a set of aircraft sensor data. The system may further include an actuator control component configured to synchronously receive and vote on the pilot sensor data and the aircraft sensor data, such that a voted output of the at least three pilot sensor channels is transmitted to a flight control computer and augmented before being transmitted to remote electronics units. The voted output of the at least three pilot sensor channels providing for the control of the aircraft surfaces coupled to the remote electronics units.

Triplex cockpit control data acquisition electronics

A flight control system includes an output device, a first processor, and a second processor. The second processor is dissimilar to the first processor. The flight control system also includes a first arbitration device coupled to the first processor and a second arbitration device coupled to the second processor. The second arbitration device is configured to coordinate transaction synchronization with the first arbitration device and the first arbitration device is configured to coordinate transaction synchronization with the second arbitration device. A comparator processor is coupled to the first arbitration device and the second arbitration device. The comparator processor is configured to compare transaction synchronized outputs of the first and second processors and the comparator processor effectuates a command to the output device if the comparison is valid.

Dissimilar processor synchronization in fly-by-wire high integrity computing platforms and displays

A method of comparing output information from dissimilar processors includes storing a task in a first memory and storing the task in a second memory at substantially the same time as the first memory. The time of the storing being is controlled by a first arbitration logic and a second arbitration logic. The method also includes receiving the task by a first processor from the first memory and receiving the task by a second processor from the memory at substantially the same time as the first processor. The time being received is controlled by a first arbitration logic and a second arbitration logic. The second processor being dissimilar to the first processor. The method further includes computing a first output by the first processor based on the task and computing a second output by the second processor based on the task. The method still further includes, synchronizing the first and second outputs so that the first and second outputs are output at substantially the same time. The synchronizing is controlled by the first and second arbitration logic.

High integrity computing via input synchronization systems and methods

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Cedar Rapids, IA, United States of America

John W Roltgen