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Array Portfolio LLC

John W Rible

Charles H Moore

Jeffrey Arthur Fox

A computer array () has a plurality of computers (). The computers () communicate with each other asynchronously, and the computers () themselves operate in a generally asynchronous manner internally. When one computer () attempts to communicate with another it goes to sleep until the other computer () is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer () can be awaiting data or instructions (). In the case of instructions, the sleeping computer () can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register () when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop () which is capable of performing a series of operations repeatedly. In one application, the sleeping computer () is awakened by an input such that it commences an action that would otherwise have required an interrupt of an otherwise active computer.

Clockless computer using a pulse generator that is triggered by an event other than a read or write instruction in place of a clock

A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.

Method and apparatus for arranging multiple processors on a semiconductor chip

A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.

Computer system and method for executing port communications without interrupting the receiving computer

A computer array () has a plurality of computers (). The computers () communicate with each other asynchronously and operate in a generally asynchronous manner internally. When one computer () attempts to communicate with another it goes to sleep until the other computer () is ready to complete the transaction, thereby saving power and reducing heat production. The instructions executed by the computers () can include a micro-loop () which is capable of performing a series of operations repeatedly. In one application, the sleeping computer () is awakened by an input such that it commences an action that would otherwise required an interrupt of an otherwise active computer. For example, one computer () can be used to monitor an input/output port of the computer array ().

Method and apparatus for monitoring inputs to an asyncrhonous, homogenous, reconfigurable computer array

A computer array () has a plurality of computers (). The computers () communicate with each other asynchronously, and the computers () themselves operate in a generally asynchronous manner internally. Instruction words () can include a micro-loop () which is capable of performing a series of operations repeatedly. In a particular example, the series of operations are included in a single instruction word (). The micro-loop () in combination with the ability of the computers () to send instruction words () to a neighboring computer () provides a powerful tool for allowing a computer () to utilize the resources of a neighboring computer ().

Processor and method for executing a program loop within an instruction word

A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.

Circular register arrays of a computer

A computer () having multiple data paths (-) connecting to other devices, which may be similar computers. A register () is provided that has bits () programmatically settable to address each of the data paths such that the computer can communicate via multiple of the data paths based on which bits are concurrently set in the register. The bits respectively represent instances of the other devices as source devices that the computer can read data from and instances of the other devices as destination devices that the computer can write data to. A single address in the register can represent both a source device and a destination device for data communicated by the computer. Optionally, multiple of the computers can be connected in series (termed a pipeline) or to form an array ().

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Santa Cruz, CA, United States of America

John W Rible