3dlabs Inc., Ltd.

John W Neave

Neil F Trevett

Malcolm E Wilson

Andrew Peter Maund

Simon James Moore

Jonathan David Salkild, Deceased

David Joseph Salkild, Heir

Iain Stuart MacNaughton

A computer system having a pixel processing unit with multiple subprocessors receives positional data defining graphical objects from the CPU and writes pixel data into the image memory, and a display driver produces an image which partially includes the rendered pixels. The pixel processor is used to access patches of multiple contiguous pixels at a time, and process them in parallel. The patches used are defined, within the overall geometry of the image, to have aligned corners. The unit is also connected to receive synchronization signals from the display driver, conditioned on whether the current line being accessed by the driver is within a specified range of lines in the image space. The unit is operable to command the pixel processing unit to write pixel data corresponding to all pixels covered by a polygon, and in response traverses portions of the image space by scanning portions of one row of patches of pixels at a time, and for some of the patches, testing only the pixels at the leading edge of the patch in the direction of scanning.

Computer system with improved pixel processing capabilities

In a demand-paged virtual memory system, the pages are arranged in the virtual memory space in groups. In order to translate an address from the virtual address space to a physical memory address space, the virtual group address component is input to a contents addressable memory (767), which outputs a group code (767), and the group code and virtual page address component (768X,Y) are input to a RAM page table (750) which outputs the page address. When the physical memory capacity is substantially smaller than the virtual address space, the CAM provides a large saving in page table size. In the case where the data-elements provide a plural-dimensional representation, for example as in pixel data, the pages include data elements which are contiguous in each of the plural dimensions in order to reduce the amount of page-swapping between the physical memory and a paging memory. The data-elements in the physical memory are accessible in parallel as contiguous patches. In order to allow parallel access of patches which are not aligned with respect to a page and therefore may fall partly on the edge of one page and partly on the edge of a page which is contiguous with the first page in the virtual memory but not in the physical memory, the addressing system determines whether a patch to be accessed has data-elements in different pages, and may then modify the addresses to the physical memory.

Virtual memory system

A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In order to allow parallel access to the memory system where possible, but permit the processors also to access different addresses, each processor is selectable to supply its respective required address (xq, yq) via the address bus to the memory system to access the memory, and each non-selected processor is operable to determine whether it requires access to the address (xq, yq) on the bus, and if so to access the memory system at the same time as the selected processor.

Data-array processing system wherein parallel processors access to the

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Los Altos, CA, United States of America

John W Neave