International Business Machines Corporation

John W Irwin

Patrick Allen Buckland

Jack E Reeder

Richard G Fogg, Jr

James D Wagoner

Phil H Hall

A memory system that includes several memory locations connected to a reading circuit that provides read access to the memory location. The memory system also includes the controller that receives control information. A writing circuit is further included that provides write access to either only a first portion of the memory locations, or simultaneously several portions of the memory locations is designated by the control information. This invention further includes a memory system that provides several memory locations for the storage of information together with the controller having a first port and a second port. The first port provides access to the memory locations in response to a first address range and the second port provides access to the memory locations in response to several address ranges wherein at least one of the address ranges of the second port is different then the address range of the first port. Still further, the invention includes a memory system having a first group of memory locations that store information in accordance with the first address range and a second group of memory locations. The two groups of memory locations are connected to a controller that provides write access to the first group of memory locations in a response to write commands having addresses within the first address range and, simultaneously writing each write command address in the second group of memory locations.

Data processing system with multi-access memory

In a serial link in which it is necessary to occupy the link before and after transmission of a frame by sending a succession idle characters having alternating disparity effects, the disparity effect of the last character in the frame is compared with the disparity effect that would be produced by a disparity flip-flop, which has continued to step during frame transmission. If the disparity effect of these two characters match, no corrective action is required in order to resume the stream of idle characters. If the disparity effect of these characters differ, the disparity flip-flop is corrected before the stream of idle characters is resumed. Disclosed is hardware logic to accomplish this disparity control following transmission of frames in a transparent mode.

Serial link transparent mode disparity control

A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. In a second mode, a display is time-shared between processors by establishing a virtual video buffer in main memory which is written into by one processor when the other processor has control of the display device. The contents of the virtual and real buffer are swapped whenever the display is reassigned to the other processor. In the third mode, co-processor data in the virtual buffer can be 'windowed' onto the display device when it is assigned to the main processor. In the fourth mode, a display assigned to the co-processor displays data being run by code that is written to the displayed on a display device with a different pel resolution. The main processor does a pel conversion operation on the data in the process of transferring the data from the virtual buffer to the real buffer.

Logical arrangement for controlling use of different system displays by

A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. The display control means is based on logic circuitry associated with the co-processor for trapping instructions having addresses within the range of those reserved for the display devices. The logic enables normal writes and reads to the video buffer to be suppressed or relocated to the virtual buffer, depending on the mode established by the main processor. A circular queue is established in memory to enable the main processor to selectively individually update the video buffer with the changes that have been made to the virtual buffer.

A data processing system having a main processing unit, a memory subsystem, and a co-processor selectively connectable to said memory subsystem through an Input/Output Channel Controller which includes a control means for arbitrating access to the I/O Bus among the co-processor and the other I/O devices connected to the Bus. Since the co-processor runs programs stored in the memory subsystem, there is a tendency for the co-processor to monopolize the bus with instruction fetch cycles, thereby excluding other I/O devices from access to the bus. The control means for arbitrating responds to requests on the basis of a linear priority scheme in which the co-processor has the lowest priority. Each device, except the co-processor, is permitted to keep control of the bus until it voluntarily relinquishes it. The co-processor, on the other hand, relinquishes control of the bus in response to a request for access by any higher operator. However, control is returned automatically to the co-processor in the absence of any other request, since the co-processor continually raises its access request line.

System for arbitrating use of I/O bus by co-processor and higher

A co-processor is connectable to a main system data bus to run software unknown to the main processor. The main processor can concurrently run other software and maintains priority over shared I/O facilities by providing trapping logic incorporated in a random access memory and dynamically loadable by the master processor which contains data related to the current useability by the co-processor of a shared I/O device. Additional logic is associated with the co-processor to manage interrupts between the co-processor and the system bus.

Processor I/O and interrupt filters allowing a co-processor to run

Optimal reservoing times of an ink jet printer are determined to be when an optimal time period exceeds a fixed maximum value, where the optimal time period is proportional: to the time since last reservoing, to the usage, and to the square of temperature changes. Specifically, the optimal time period, t-opt, is

Reservo interval determination in an ink jet system

Printer having a sheet feed and drum transport assembly, an exit assembly and at least one dryer. Various print parameters or conditions are monitored relating to the drying of the ink on print media. These print parameters include print data density, ink characteristics and ambient humidity. The monitored print parameters are used to control the drying. In addition the monitored print parameters are used to control the detaching of the print media from a rotary transport. In this manner, the printer approaches an optimization of the drying and detaching function with respect to time and energy.

Method and apparatus for controlling drying and detaching of printed

Printer having a sheet feed and drum transport assembly and an array transport assembly, these assemblies having critical operating parameters whose profile is measured during a nonprinting cycle executed for that purpose. These critical operating parameter values are sorted and used as the values of the respective critical parameters during the printing cycles after the profiling cycle. The values may be updated according to detected variances occurring during the printing cycles. In addition, the value of the paper position is determined during an initial printing cycle and stored and used in subsequent cycles.

System for controlling and sequencing a printer

The disclosure teaches that a cyclable program loop can be alternatively used to selectively initiate subprograms or as a timing signal generator, the latter preferably in a maintenance mode of a machine in which the loop resides. A programmable machine has a cyclable program loop with a preset number of program steps. First sequences of internal machine operations cooperate with said loop such that, based upon detection of predetermined status signals, one of a plurality of object programs may be initiated. In a second mode of operation, the status signals are suppressed; and the cyclable program loop is selectively used in a second mode or as in said first mode. In a preferred form, the second mode, the cyclable program loop, is a timing cycle usable in connection with maintenance procedures on the programmable machine. At the expiration of each timing cycle, the loop supplies a reference signal for operating a second set of internal machine functions. Such timing operations are preferably interleaved with first mode functions.

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Georgetown, TX, United States of America

John W Irwin