Lsi Logic Corporation

Olympus Optical Company, Ltd.

Symetrix Corporation

Other

Lsi Lgoic Corporation

John W Gregory

Derryl D J Allman

Derryl D Allman

David W Daniel

Carlos Alberto Paz De Araujo

Larry D McMillan

Takashi Mihara

Hiroyuki Yoshimori

John J Seliskar

James P Yakura

Dim Lee Kwong

Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.

Metal-insulator-metal capacitor formed by damascene processes between metal interconnect layers and method of forming same

A method of planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom is described. The method includes the step of positioning a fluid flow surface relative to the wafer surface so that (i) a space is defined between the wafer surface and the fluid flow surface, and (ii) the elevated portion of the semiconductor wafer is positioned in the space. The method also includes the step of advancing a fluid within the space so that the fluid contacts and erodes the elevated portion of the semiconductor wafer. An associated apparatus for planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom is also described.

Method and apparatus for planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom

An arrangement for planarizing a surface of a semiconductor wafer. The arrangement includes a planarizing member having a planarizing surface configured to be (i) positioned in contact with and (ii) moved relative to the surface of the semiconductor wafer so as to remove material from the surface of the semiconductor wafer such that the surface of the semiconductor wafer is planarized. The arrangement also includes an adherence promoting ligand chemically bonded to the planarizing surface of the planarizing member. The arrangement further includes an abrasion particle chemically bonded to the adherence promoting ligand such that the abrasion particle is attached to the planarizing surface of the planarizing member. The arrangement also includes a conditioning bar having a conditioning portion positioned in contact with a wafer track defined on the planarizing member. The conditioning portion is configured so that the conditioning portion extends completely across the wafer track. The arrangement still further includes a wafer carrier which (i) urges the surface of the semiconductor wafer against the planarizing surface at a first pressure for a first period of time and (ii) urges the surface of the semiconductor wafer against the planarizing surface at a second pressure for a second period of time. The first pressure is greater than the second pressure such that slurry is advanced from an outer periphery of the semiconductor wafer toward a center portion of the semiconductor wafer. An associated method of planarizing a surface of a semiconductor wafer is also disclosed.

Apparatus and method for planarizing the surface of a semiconductor wafer

This invention comprises an improved method of planarizing, an integrated circuit formed onto a semiconductor substrate and the planarized semiconductor substrate. Improved planarity is accomplished through the use a first and second stop layer separated by a filler layer. A first stop layer is used to define active and trench regions. A filler layer is then applied over the surface of the substrate and a second stop layer is applied on top of the filler layer. The second stop layer is patterned through etching. The pattern etched into the second stop layer is used to control chemical mechanical polishing that planarizes the surface. Patterns can be a reverse image of an active mask or a continuous pattern. In addition CMP can be used to create a condition of equilibrium planarity before the second stop layer is applied. The stop layers can comprise polysilicon, silicon nitride, or another material that is harder than a dielectric oxide material used as filler material. In addition a polysilicon stop layer may be exposed to a thermal cycle and oxidized into silicon dioxide after some degree of planarization to further regulate chemical mechanical polishing.

Substrate planarization with a chemical mechanical polishing stop layer

A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system

A method of planarizing a semiconductor that includes (i) a substrate material, (ii) a first reflective substance positioned on the substrate material, (iii) an intermediate material positioned on the first reflective substance, wherein a channel is defined in a structure which includes the substrate, the first reflective substance, and the intermediate material, and (iv) a second reflective substance positioned on the intermediate material and in the channel is disclosed. The method includes the steps of (i) directing light onto a first side of the semiconductor wafer, (ii) polishing the first side of the semiconductor wafer in order to remove matter therefrom and expose the first reflective substance, the matter including the second reflective substance and the intermediate material, (iii) detecting when light directed in the directing step is simultaneously reflected by (A) the first reflective substance positioned on the substrate, and (B) the second reflective substance positioned in the channel, and generating an endpoint detection signal in response thereto, and (iv) terminating the polishing step in response to generation of the endpoint detection signal. An associated apparatus is also disclosed.

Apparatus and method of planarizing a semiconductor wafer that includes a first reflective substance and a second reflective substance

The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.

Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking

A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes polishing the first layer of the semiconductor wafer with a polishing surface having a chemical slurry positioned thereon. The polishing step causes an infrared spectrum to be emitted through the semiconductor wafer. Another step of the method includes detecting a rate of change of intensity level of the infrared spectrum and generating a control signal in response thereto. The method also includes halting the polishing step in response to generation of the control signal. Polishing systems are also disclosed which determine a polishing endpoint for a semiconductor wafer based upon an infrared spectrum generated due to a chemical slurry reacting with the semiconductor wafer.

Method and apparatus for detecting a polishing endpoint based upon infrared signals

The present invention provides a method and apparatus for conditioning a polishing pad in which slurry is directed under pressure at the polishing pad. Additionally, energy (i.e., ultrasonic energy) may be added to the slurry as it is directed towards the polishing pad, wherein embedded material in the polishing pad is removed or dislodged.

Subsonic to supersonic and ultrasonic conditioning of a polishing pad in a chemical mechanical polishing apparatus

A method of planarizing a semiconductor wafer to a distance from a semiconductor substrate of the wafer is disclosed. The method includes the step of forming in the wafer a metallic reporting substance that is at the predetermined distance from the substrate of the wafer. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. The method further includes the step of utilizing an atomic absorption spectroscopic technique to detect the presence of the metallic reporting substance in the material removed from the wafer. Moreover, the method includes the step of terminating the polishing step in response to the detection of the metallic reporting substance. An associated apparatus for polishing a semiconductor wafer down to a metallic reporting substance of the wafer is also described.

Apparatus and method of detecting a polishing endpoint layer of a

The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.

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Colorado Springs, CO, United States of America

John W Gregory