International Business Machines Corporation

John W Golz

Toshiaki Kirihata

Hoki Kim

David R Hanson

Gregory J Fredeman

Teresa Jacqueline Wu

Pooja R Batra

Subramanian Srikanteswara Iyer

Christopher Joseph Waskiewicz

Paul Christian Parries

Spyridon Skordas

Douglas C La Tulipe, Jr

Kevin R Winstel

Joyce C Liu

Mark David Jacunski

Jin J Wu

Charles W Koburger, Iii

Qinghuang Lin

Babar Ali Khan

Bomy A Chen

Chienfan Yu

Rebecca D Mih

Alan C Thomas

Chorng-Lii Hwang

Jeffrey J Brown

George A Kaplita

Robert A Coles

Senthil K Srinivasan

Fumihiko Satoh

John Zhu

James C Brighten

David R Hansen

Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.

Double-sided segmented line architecture in 3D integration

The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.

Combination of TSV and back side wiring in 3D integration

A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

Low power manager for standby operation of memory system

Low power manager for standby operation of a memory system

In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

Dynamic random access memory with smart refresh scheduler

A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.

Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology

As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.

Bi-directional read write data structure and method for memory

An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.

Structure and method of making three finger folded field effect transistors having shared junctions

Gain cells adapted to trench capacitor technology and memory array configured with these gain cells are described. The 3T and 2T gain cells of the present invention include a trench capacitor attached to a storage node such that the storage voltage is maintained for a long retention time. The gate of the gain transistor and the trench capacitor are placed alongside the read and write wordline. This arrangement makes it possible to have the gain transistor directly coupled to the trench capacitor, resulting in a smaller cell size. The memory cell includes a first transistor provided with a gate, a source, and a drain respectively coupled to a read wordline, a first node, and a read bitline; a second transistor having a gate, a source, and a drain respectively coupled to a storage node, to a voltage source, and to the first node; a third transistor having a gate, a source, and a drain respectively coupled to a write wordline, the storage node, and a write bitline; and a capacitor having a first terminal connected to the storage node and a second terminal connected to a voltage source.

Gain cell structure with deep trench capacitor

As disclosed herein, a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integrated circuit. The method includes depositing a feature layer over a substrate and a hardmask material layer thereover. Photoresist patterns are then formed in the first and second portions with a critical dimension mask, and are then used to etch the hardmask material layer into hardmask patterns. Sidewall spacers are provided on sidewalls of the hardmask patterns in the second portion. Then, the feature layer is simultaneously etched in both first and second portions, using the hardmask patterns in the first portion to define features having a first width, and using the hardmask patterns and the sidewall spacers in the second portion to define features having a second width.

Method of forming active devices of different gatelengths using lithographic printed gate images of same length

A MOSFET device and method, the method involves forming the MOSFET device by selectively doping bordering channel regions in the device such that, in operation, the threshold, or turn-on, voltage is equalized across the channel. The device structure comprises a self-aligned channel edge implant region for equalizing threshold voltages in the channel edge region with threshold voltages in the channel interior region, thereby virtually eliminating sub-threshold leakage current in low voltage applications.

MOSFET with self-aligned channel edge implant and method

A method for planarizing a layer of photoresist on a substrate. The layer of photoresist is exposed to wavelengths of radiation that the photoresist is sensitive to. The radiation is directed at the layer of photoresist at an oblique angle with respect to a major dimension of the layer of photoresist. The photoresist is developed.

Method and apparatus for resist planarization

A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

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Manassas, VA, United States of America

John W Golz