Other

Digital Equipment Corporation

John W Eng

Thomas Courtenay Porcher

Robert S DiNitto

Charles S Namias

David B Hughes

A method and system are disclosed for enabling point-to-point and multicast communication in a multiple access network using three types of communication channels, namely, one or more upstream payload channels, one or more upstream control channels and one or more downstream channels. Each channel illustratively is divided into slots or mini-slots. Each upstream payload channel is assigned for carrying upstream directed payload bitstreams from stations to a central controller. The central controller has an independent receiver for each upstream channel for simultaneous reception of control and payload bitstreams. Each station has at least one frequency agile programmable transmitter for sequential transmission of control and payload bitstreams or separate upstream control and payload channel transmitters, respectively, for simultaneous transmission of control and payload bitstreams. Each upstream control channel is assigned for carrying upstream directed control bitstreams, such as reservation request bitstreams requesting reservation of time slots of the upstream payload channel, from the stations to the central controller. At least one downstream channel is assigned for carrying at least downstream directed control bitstreams, such as bitstreams containing network configuration acknowledgments, collision, status of reservation request, and also containing indications of assigned slots in the upstream payload channel, from the central controller to the stations. The downstream channel may also illustratively carry payload bitstreams.

Method and apparatus for reserving resources of one or more multiple access communication channels

A method and system are disclosed for enabling point-to-point and multicast communication in a network using three types of communication channels, namely, one or more upstream payload channels, one or more upstream control channels and one or more downstream channels. At least the upstream control and upstream payload channels can carry bitstreams simultaneously; a bitstream may be simultaneously carried on the upstream control and upstream payload channels of a shared medium during overlapping periods of time. Each channel illustratively is divided into slots or mini-slots. Each upstream payload channel is assigned for carrying upstream directed payload bitstreams from stations to a central controller. Each upstream control channel is assigned for carrying upstream directed control bitstreams, such as reservation request bitstreams requesting reservation of time slots of the upstream payload channel, from the stations to the central controller. At least one downstream channel is assigned for carrying at least downstream directed control bitstreams, such as bitstreams containing acknowledgments, collision, status of reservation request, and also containing indications of assigned slots in the upstream payload channel, from the central controller to the stations. The downstream channel may also illustratively carry payload bitstreams.

High capacity reservation multiple access network with multiple shared

This invention encompasses pharmaceutical compositions containing exendin-3 or exendin-4, fragments thereof, or any combination thereof, and methods for the treatment of diabetes mellitus and the prevention of hyperglycemia.

Exendin-3 and exendin-4 polypeptides, and pharmaceutical compositions

The present invention includes a microprocessor which acts to generate groups of its signals from its read only memory (ROM) thereby forming character representations of groups of coded signals, such as ASCII coded signals, coming from a main data processing device. The groups of bit signals are temporarily stored in a buffer which at a subsequent time transmits, in parallel, groups of said bit signals to a bit map memory through some logic circuitry. The group, or block, transfer of said bit signals in parallel, occurs during horizontal or vertical blank periods. The parallel transfer during the blank periods provides part of the basis for acceleration of the data to a display device as compared with the prior art. In addition, the microprocessor provides address information signals to a graphic display controller, which in turn provides starting addresses, for the locations of the bit signals. In addition a bit map memory device is employed to provide pixel information to a CRT display device to create the characters which are to be shown.

Arrangement for providing data signals for a data display system

The present invention is employed in a system which has a bit map memory connected to a CRT display device and the CRT display device can display a fixed region of information and a scrollable region of information. In a preferred embodiment, the system uses a graphic display control circuit to change starting addresses and length ending values of the fixed and scrollable regions in the bit map memory. By changing the starting address one scan line per frame, without any actual transfer of data in memory, from one location to another location, the present system effects a 'smooth' scroll. The system is able to scroll upward and downward. The system uses logic circuitry to load an off screen segment of the bit map memory with additional scrollable information, so that (in an upward scroll load) as a top line of the scrollable information region is no longer displayed, new information will be displayed at the bottom line of said scrollable region. On the other hand during a downward scroll, a bottom line of information on the scrollable region of the screen will fade out and new information is added, from the off screen region, of the bit map memory to provide information for a new top line. In addition the system has the ability to reorganize the information in the bit map memory in the event the size or location of the fixed region is to be altered.

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Southborough, MA, United States of America

John W Eng