Motorola Corporation

Other

Freescale Semiconductor,inc.

Prairiecomm, Inc.

John W Diehl

Henry L Kazecki

Wayne H Bradley

James L Porter

Thomas J Walczak

Stephen V Cahill

Steven H Goode

Robert I Greene

A receiver () comprises a non-equalizing demodulator (), an equalizing demodulator () and an output control selector (). The non-equalizing demodulator () receives a modulated signal () and demodulates the modulated signal () to produce a first digital bit stream (). The equalizing demodulator () receives the modulated signal () and equalizes and demodulates the modulated signal () to produce a second digital bit stream (). The output control selector (), coupled to the non-equalizing demodulator () and the equalizing demodulator (), selectively delivers a first one of the first digital bit stream () and the second digital bit stream () for at least a predetermined period of time () before selectively delivering a second one of the first digital bit stream () and the second digital bit stream () responsive to a predetermined decision criterion (e.g., bit error rate). The first one of the first digital bit stream () and the second digital bit stream () is different from the second one of the first digital bit stream () and the second digital bit stream ().

Receiver having equalizing demodulator and a non-equalizing demodulator and method for controlling the same

A receiver generates two metrics, one that is used to control the gain of an amplifier and the other that is used to determine the presence of narrowband interference, such as IMD. The two metrics may represent analog-to-digital converter (A/D) saturation and average signal strength, either of which may be used to control gain or to detect the presence of narrowband interference.

Receiver having gain control and narrowband interference detection

In a radiotelephone ( ), a channel estimator ( ) receives a time division multiple access (TDMA) information signal ( ) including a synchronous codeword ( ), formed of a first subset of seven sequential symbols ( ) followed by a second subset of seven sequential symbols ( ), followed by a data sequence ( ) formed of multiple sequential symbols. The channel estimator ( ) uses the first subset ( ) to train, via initializing ( ) and updating ( ), the channel estimator to stabilize the channel estimate. The channel estimator ( ) uses the second subset ( ) to train, via initializing ( ) and updating ( ), the predictor to improve the future accuracy of the channel estimate. The channel estimator ( ) then tracks ( ) the channel estimate over the data sequence ( ) by updating the channel estimator and the predictor over the data sequence ( ), without substantially affecting the stability of the channel estimate or the future accuracy of the channel estimate.

Channel estimator and method therefor

A demodulation subsystem includes an equalizing demodulator and a non-equalization demodulator, each of which receive a baseband signal, and an output control selector that selects the output of one of the equalizing demodulator and the non-equalizing demodulator based on a bit error rate of the signal.

Dual mode receiver

A rectangular to phase converter (201) includes a first converter circuit (201B) which limits signals to a predetermined level. A phase selector (259) selects a relative phase from the limited signals. According to one aspect of the invention, input rectangular coordinate signals are mapped to the first quadrant in a first quadrant mapping circuit (201A) before the first quadrant signals are limited and the relative phase signal is returned to the original quadrant by an original quadrant mapping circuit (260).

Method and converter for converting rectangular signals to phase signals

A complex constellation point multiplier (600) multiplies a complex number by a point in a digital modulation constellation. The desired constellation point is mapped to a digital control word. The complex number is connected to multiplicand input nodes (610, 615) and the digital control word is connected to control input nodes (620, 623, 626). Via logic gates (602, 603, 605, 606, 607, 609), the control word controls switches (651-658) and simple arithmetic blocks, such as accumulators (650, 659), scaler blocks (663, 665), and negation blocks (643, 646), to generate an output complex number that is the product of the input complex number and the constellation point. This complex constellation point multiplier provides a lower size and lower power-consumption alternative to traditional complex number multipliers.

Complex constellation point multiplier

An apparatus and method generates a shaped transition between the minimum and maximum output power levels of a transmitter (500). When the transmitter is turned on a stepped transition (415) is generated at the beginning (3) of the transition region (409) followed by a shaped transition (417) to the end (6) of the transition region (409). When the transmitter (500) is turned off a shaped transition region (417') is generated at the beginning (162) of the transition region (411) followed by a stepped transition (415') at the end (3) of the transition region (411). The stepped transition (415 or 415') is generated by adjusting a voltage controlled attenuator (545) and the bias of a power amplifier (545) in the transmitter (500). The shaped transition (417 or 417') is generated by processing transmitted information through finite impulse response filters (507 or 509) before or after the time slot permitted for transmitting information.

Apparatus and method for generating a transition between the on and off

A diversity receiver (200) recovers clock information from different versions (301, 302) of a transmitted signal (106). The diversity receiver (200) receives the different versions (301, 302), converts the versions (301, 302) into samples (307, 317) via a common sampling clock (309). The receiver (200) then correlates the samples (307, 317) with like synchronization patterns and uses clock information from the received version (307 or 317) which gives the greatest correlation output signal (504, 506) for data detection in one of two detectors (323, 326). The choice of detectors (323, 326) is determined by the diversity receiver (200) by counting the total number of bit-differences output by detectors (323, 326) over a predetermined time period and comparing the total bit-differences with a number represented by a threshold signal (330).

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Elmhurst, IL, United States of America

John W Diehl