S3 Graphics Co., Ltd.

S3 Incorporated, Inc.

John W Brothers

Zhou Hong

Roger Swanson

Daniel Hung

A device calculates a display color based on a true color, a fog color, and a distance z. The device uses two single-port memories, an arithmetic circuit, and a color blending circuit. Based on the distance z, two sampled values of a fog function are read from the single-port memories, one value from each memory. The arithmetic circuit calculates an approximate value of the fog function corresponding to the distance z based on the two sampled values of the fog function. The color blending circuit calculates the display color by blending the true color and the fog color according to the approximate value of the fog function.

Device and method for blending true colors and fog colors to generate display colors

A method of providing specular highlights to 3D graphics using Phong illumination calculations spaces the pixels subject to the calculations apart in direct relationship to the number of lights contributing to the highlights. Linear, quadratic, or cubic attenuation is then applied to interpolate the values for the pixels not subject to the calculations.

Method and apparatus for interpolative, adaptive illumination in 3D graphics

A write blocking accelerator provides maximum concurrency between a central processing unit (CPU) and the accelerator by allowing writes to the front buffer of a dual-buffered system. The CPU issues a series of drawing commands followed by a 'page flip' command. When a command parser within the accelerator receives a page flip command, it notifies a screen refresh unit reading from the front buffer that the command was received. The screen refresh unit signals a memory interface unit (MIU) to enter a write blocking mode and provides the address of the current line in the front buffer from which the screen refresh unit is reading, and the address of the last line in the front buffer. The MIU blocks all writes from drawing engines that fall into the range defined between the two addresses. The screen refresh sends updated front buffer addresses to the MIU as display data is read out of the front buffer. Accordingly, the blocked address range constantly shrinks until all writes are allowed by the MIU. At that point, the screen refresh unit signals the MIU that it has reached vertical retrace and the MIU exits write blocking mode.

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Palo Alto, CA, United States of America

John W Brothers