Nvidia Corporation

John W Berendsen

Karim Abdalla

Paul S Heckbert

Emmett Michael Kilgariff

Michael J M Toksvig

Alexander Lev Minkin

Joel James McCormack

Robert William Chapman

Luke Y Chang

Bo Hong

Radoslav Danilak

Walter E Donovan

Rui Manuel Bastos

Lordson L Yue

Walter Donavan

Circuits, methods, and apparatus that reduce the power consumed by data transfers initiated by a USB host controller. Peripheral devices on a USB network are accessed with a reduced frequency in order to save power dissipated by a CPU and other circuits when reading data needed by the host controller. Instead of possibly accessing devices each frame, peripheral devices are accessed during some frames, and not accessed during others. A USB host controller may have two or more modes, such as a low power mode and a regular mode. In the low power mode, USB devices are accessed during fewer than all frames, in the regular mode, USB devices are possibly accessed each frame. Mode selection may depend on whether battery power is used.

Reducing system power consumption due to USB host controllers

Circuits, methods, and apparatus that reduce the power consumed by transactions initiated by a number of USB host controllers. Peripheral devices on a number of USB networks are accessed in a coordinated manner in order to reduce power dissipated by a CPU and other circuits when reading data needed by the host controllers. The resulting memory reads are temporally clustered. This allows the CPU to process a greater number of requests each time it leaves a low-power state. As a result, the CPU may possibly remain in a sleep state for a longer period of time, thus saving power. This is accomplished at the host controller level by synchronizing the time frames used by each host controller in a system. The synchronizing signal may be one or more bits of a frame count provided by one host controller to a number of other frame controllers.

Synchronizing multiple USB controllers to reduce power

Systems and methods used for bilinear texture filtering may also be used to perform font filtering. Font data stored as a texture is read from memory in blocks that are coarsely aligned. Font alignment units may be used to provide a finely aligned region of the font data within a font filter footprint. The finely aligned region is then filtered using bilinear filtering to produce font coverage information representing a grayscale value for a pixel. Using existing bilinear filtering engines in conjunction with font alignment and sample units reduces the need for having a specific engine to perform each of the font filtering operations, possibly saving die area in a graphics system.

Font filter using bilinear interpolation

Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Reconfigurable high-performance texture pipeline with advanced filtering

Reconfigurable high performance texture pipeline with advanced filtering

Systems and methods for processing linear colorspace data may be reused to process nonlinear colorspace data at a comparable performance level while maintaining the precision of the nonlinear colorspace data. Nonlinear colorspace data is converted to a compact floating point format in a linear colorspace used by conventional graphics processors. The compact floating point format includes an 8 bit explicit mantissa (without an implied leading one) and a 3 bit exponent to maintain the precision of the nonlinear colorspace data. The 8 bit mantissa may be processed by conventional texture filtering units designed to process 8 bit (fixed or floating point) color values. The 3 bit exponent may by processed by conventional texture filtering units designed to process floating point color values.

Conversion of data in an sRGB format to a compact floating point format

Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port for read operations and for write operations. Either a single read or a single write operation is performed for a given clock via the single port. Moreover, the single-port RAM serially performs N read operations and M write operations associated with a data group using a clock phase of (N+M) clock phases generated from a clock. In another embodiment, a semiconductor device includes the architecture for compact multi-ported register file. The semiconductor device comprises a plurality of register files. Each register file comprises a RAM comprising a port for read operations and for write operations. Moreover, each RAM serially performs N read operations and M write operations associated with one of a plurality of data groups using a corresponding clock phase of (N+M) clock phases generated from a clock. Further, the semiconductor device comprises an input staging unit for staging write data of one or more of the write operations. Continuing, the semiconductor device comprises an output staging unit for staging read data of one or more of the read operations. The semiconductor device can be a graphics processing unit (GPU).

Architecture for compact multi-ported register file

Circuits, methods, and apparatus that increase utilization of available USB bandwidth, limit the amount of data accessed from memory, and provide for parallel requests for data from memory. An exemplary embodiment of the present invention caches a pointer for each transfer descriptor in a periodic and async schedule. Several transfer descriptors are also cached. Caching pointers reduces the time needed to organize the needed transfer descriptors to be transmitted. Caching several transfer descriptors eliminates the need to access the main memory each time they are needed. Also, if more transfer descriptors are needed beyond those in cache, memory requests for multiple transfer descriptors may be done in parallel since their pointers are available in cache.

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CA

John W Berendsen