International Business Machines Corporation

Microsoft Technology Licensing, LLC

Advanced Micro Devices Corporation

Cagent Technologies, Inc.

John Victor Sell

James Allan Kahle

Aubrey Deene Ogden

Albert J Loper, Jr

Eric Oliver Mejdrich

Ling Tony Chen

Soummya Mallick

Jonathan E Lange

Cang Ngoc Tran

Douglas Christopher Hester

Nhon Toai Quach

Susan Elizabeth Carrie

Jeffrey Andrews

Kevin Po

Gregory L Limes

A data processing machine is configured to automatically keep track of hypervisor given pointers pointing to respective and newly allocated areas of memory and to automatically keep track of corresponding copies or derivatives of the given pointers. A unique allocation identifier is generated for each newly allocated area. The allocation identifier is appended to a valid ID's holding list. All pointers pointing to the allocated area are tracked by a protected pointers tracking table. Additionally, a multi-input associative cache stores entries for recently used ones of the protected pointers where the entries include the respective allocation identifiers of the pointers. All pointers to a given, de-allocated area can be invalidated by deleting their entries form the multi-input associative cache and by deleting the corresponding unique allocation identifier from the valid ID's holding list.

Protected pointers

The subject disclosure is directed towards using one or more of hardware, a hypervisor, and privileged mode code to prevent system mode code from accessing user mode data and/or running user mode code at the system privilege level, or vice-versa. Also described is (in systems with a hypervisor) preventing non-hypervisor code from running in hypervisor mode or accessing hypervisor-only data, or vice-versa. A register maintained by hardware, hypervisor, or system mode code contains data access and execution polices for different chunks of addressable space with respect to which requesting entities (hypervisor mode code, system mode code, user mode code) have access to or can execute code in a given chunk. When a request to execute code or access data with respect to an address is received, the request is processed to determine to which chunk the address corresponds. The policy for that chunk is evaluated to determine whether to allow or deny the request.

Secure privilege level execution and access protection

A data processing machine is configured to include one or more buried memory zones that are not intelligibly accessible to user software and to operating system software or hypervisor software within the data processing machine. At least one of hardware and firmware are configured to intelligibly access at least one of the buried memory zones so as to store therein, metadata defining one or more extents of a respective one or more protected regions (PR's) that are constituted in other memory areas of the data processing machine. The stored metadata defines constraints for the corresponding PR's including at least one of corresponding operational constraints and/or operational requirements that respectively constrain the operations performed by or on the data of the PR's.

Protected regions

Systems and methods for applying a fine-grained QoS logic are provided. The system may include a memory controller, the memory controller configured to receive memory access requests from a plurality of masters via a bus fabric. The memory controller determines the priority class of each of the plurality of masters, and further determines the amount of memory data bus bandwidth consumed by each master on the memory data bus. Based on the priority class assigned to each of the masters and the amount of memory data bus bandwidth consumed by each master, the memory controller applies a fine-grained QoS logic to compute a schedule for the memory requests. Based on this schedule, the memory controller converts the memory requests to memory commands, sends the memory commands to a memory device via a memory command bus, and receives a response from the memory device via a memory data bus.

Fine-grained bandwidth provisioning in a memory controller

A computer graphics processing system includes a graphics processor and a computer memory responsive to the graphics processor. The computer memory includes an image depth buffer and a hierarchical image depth buffer. The hierarchical image depth buffer contains data items that identify a nearest depth value and a farthest depth value for a plurality of image depth buffer entries associated with a plurality of corresponding pixels.

Computer graphics processing system, computer memory, and method of use with computer graphics processing system utilizing hierarchical image depth buffer

The present invention relates to a computer graphics processing system, a memory and a method for use in connection with the computer graphics processing system. In one embodiment, the computer graphics processing system includes a graphics processor and a computer memory responsive to the graphics processor. The computer memory includes an image depth buffer and a hierarchical image depth buffer. The hierarchical image depth buffer contains data items that identify a nearest depth value and a farthest depth value for a plurality of image depth buffer entries associated with a plurality of corresponding pixels. In one embodiment, the method is for use in rendering a portion of an object onto a two-dimensional image plane. A disclosed method includes the steps of identifying a selected pixel corresponding to the portion of the object to be rendered, reading data items from a hierarchical image depth buffer, and performing a comparison between the selected pixel and the data items to make a pixel visibility determination. The data items include a near depth value and a far depth value. The hierarchical image depth buffer is associated with a plurality of depth values for a set of pixels where the set of pixels includes the selected pixel.

A method and mechanism for managing graphics data. A graphics unit is coupled to share a cache and a memory with a processor. The graphics unit is configured to partition rendered images into a plurality of subset areas. During the rendering of an image, data corresponding to subset areas of an image which require a relatively high number of accesses is deemed cacheable for a subsequent rendering. During a subsequent image rendering, if the graphics unit is required to evict data from a local buffer, the evicted data is only stored in the shared cache if a prior rendering indicated that the corresponding data is cacheable.

CPU and graphics unit with shared cache

A method for maintaining memory coherency in a data processing system is disclosed. The data processing system includes a memory system having a dual bus memory controller, which is coupled to a first bus through a first bus master and a second bus coupled to a second bus master. The method maintains memory coherency by snooping across either the first or second bus for attributes on an address/data multiplex bus in the data processing unit. To determine when a snoop operation is required, the system begins by requesting access to either of the two buses through the dual bus memory controller. Once the control of the bus has been granted upon request data is transferred using the master bus controller. It is upon the receipt of an invalid data signal while transferring data across the bus that the snoop activity begins. The snoop is injected only after an invalid data signal is received and a last snoop injection can occur only before a last read data is read.

Method for maintaining memory coherency in a computer system having a

A plurality of 'snoop advisory' bits are maintained by snoop management circuitry externally to the processor structure. Each snoop advisory bit corresponds to a respective 'snoop advisory page' of the memory address space. Three parallel processes take place with respect to these bits. First, in response to each read access by the processor structure, if the read access is of a predetermined type (such as a cache line fill operation with intent to modify), snoop management circuitry writes a 'snoop yes' value into the snoop advisory cell corresponding to the snoop advisory page which includes the address of the processor's access. Second, in response to each access by another device which shares the address space with the processor structure, a snoop request is issued to the processor structure, but only if the snoop advisory cell corresponding to the snoop advisory page which includes the address of the device's access, contains the 'snoop yes' value. Otherwise, the device is allowed to perform its access directly to the memory structure without issuing a snoop request. Third, on a recurrent basis, the processor internal cache is synchronized with the memory structure and the system writes a 'snoop no' value into each of the snoop advisory bits to clear them. Synchronization can involve performing a write-back on each cache line which is in a modified state, and/or invalidating each line in the cache.

Method and apparatus for managing snoop requests using snoop advisory

A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execution of such an instruction is initiated an enable special access (ESA) instruction is executed as an entry point to that instruction or group of instructions. A portion of the machine state register for the data processing system is stored and the machine state register is then modified as follows: a problem bit is set, changing the execution privilege state to 'supervisor;' external interrupts are disabled; and access privilege state bit is set; and, a special access mode bit is set, allowing execution of special instructions. The instructions which execute the selected privileged operations within the protected memory space are then executed. A disable special access (DSA) instruction is then executed which restores the bits within the machine state register which were modified during the ESA instruction. The ESA and DSA instructions are implemented without modifying the instruction stream by utilizing user level procedure calls, thereby reducing the overhead of the branch table necessary to determine the desired execution path.

Method and system for enhanced management operation utilizing intermixed

A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.

Method and system for selective support of non-architected instructions

A method and system for efficient memory management in a data processing system which utilizes a memory management unit to translate effective addresses into real addresses within a translation lookaside buffer is disclosed. During a first mode of operation a selected number of effective address identifiers are stored in the translation lookaside buffer. In association with each virtual address identifier is a corresponding real address entry for a single memory block wherein selected virtual addresses may be translated into corresponding real addresses utilizing the translation lookaside buffer. In a second mode of operation, a selected number of virtual address identifiers are stored in a translation lookaside buffer and each virtual address identifier has a number of protection bits stored in association therewith, wherein each protection bit is indicative of a protection status for a large number of contiguous memory blocks beginning with the associated virtual address identifier, wherein memory block protection may be provided for a large number of memory blocks utilizing a fixed size translation lookaside buffer.

Method and system for efficient memory management in a data processing

A protocol and system for providing a next read address during an address phase of a write transaction in a data cache unit in a processing unit is disclosed. The processing unit includes the data cache unit and an instruction cache unit both coupled to an address bus and a data bus, respectively. The two buses are further connected to a system memory controller separate from the microprocessor. The protocol and system provide for next read address and a next transaction during the address phase in a current write transaction. The protocol loads a pre-fetched address within a current data transaction and then generates a next line fill address using the pre-fetched address which is concatenated to the current data transaction. The pre-fetched address is used to generate a next line fill address. The line fill address is generated upon determining if a cache read miss has occurred and if so, copying a modified cache line back to the main system memory and then loading the missed cache read line into the internal cache from the system memory controller.

Growing community of inventors

Los Altos, CA, United States of America

John Victor Sell