Emc Corporation

Dell Products Inc.

Emc IP Holding Company LLC

Emc Coropration

John Victor Burroughs

Stephen Edward Strickland

Timothy Dorr

Matthew H Long

Michael Robillard

Douglas E Peeke

John Kevin Bowman

Bassem N Bishay

Joseph P King

Steven D Sardella

Robert M Beauchamp

Adrianna D Bailey

Daniel Albert Dufresne, Ii

Daniel Savilonis

Morrie Gasser

Albert F Beinor, Jr

James Marriot Guyer

James W Espy

Steven R Cieluch

Ryan Cartland McDaniel

Maida Boudreau

David Boudreau

John P Didier

Michael A Faulkner

James Creighton Tryhubczak

Clifford Lim

Gordon A Frye

Richard John Boyle

Bassem Bishay

David F Ouellette

Jim H Street

Samuel Zeman

Michael Salerno, Jr

A storage controller has an operating system (OS) and power control firmware configured to manage use of battery power during a power outage event. The OS specifies to the power control firmware first and second sets of physical components that should be shed by power control firmware during a two-phase vault process. Upon a power failure, the power control firmware turns off power to the first set of physical components and notifies the OS of the power failure. The OS determines whether to abort or continue the vault process. If the OS aborts the vault process, the power control firmware restores power to the first set of physical components. If the OS continues the vault process, the power control firmware turns off power to the second set of physical components, the OS saves application state, and moves all data from volatile memory to persistent memory.

Maintaining data integrity through power loss with operating system control

A system for controlling data communications, comprising an enclosure management processor configured to generate a peripheral component interconnect express reset command and a chip reset command. A re-timer configured to receive the peripheral component interconnect express reset command and the chip reset command and to control a communications port in response to the peripheral component interconnect express reset command and the chip reset command. The communications port configured to reset in response to a control signal from the re-timer.

PCIe link management without sideband signals

A method and computer program product for determining an internal temperature of a computing device, a power consumption factor for the computing device, and an airflow factor for the computing device. An approximated ambient air temperature is generated based upon the internal temperature, power consumption factor, and the airflow factor. A workload factor is determined for the computing device and a fan speed for the computing device is controlled based at least in part upon the approximated ambient air temperature and the workload factor.

System and method for controlling fan speed

A system having: a midplane having air flow channels therein; a disk drive mounted to a first side of the midplane; and a temperature sensors mounted to the midplane. The system includes a pair of electrical chassis connected to a second side of the midplane. A first one of the chassis has therein: a fan; and a fan controller for controlling speed of the fan in response to a temperature control signal. A second one of the chassis has therein: a microprocessor for: detecting temperature signals produced by the temperature sensors; comparing differences between the detected temperature signals; and selecting one of the detected temperature control signal from the compared differences as the temperature control signal. A faulty one of the temperature sensors is detected by: selecting one of the detected temperature control signal as the faulty one of the plurality of temperature sensors from the compared differences.

Method for controlling cooling in a data storage system

A data storage system includes a first storage processor for storing and retrieving data from a data storage array for at least one host computer; a second storage processor, coupled to the first storage processor by a communication link, for storing and retrieving data from the data storage array for the at least one host computer; a number M of multiplexers, M being greater than one, each of the multiplexers being coupled to the first storage processor and the second storage processor for receiving data signals from the first storage processor and the second storage processor and transmitting the data signals to a disk drive device; a number A of arbiters, each being coupled to the first storage processor, the second storage processor and a number N of the plurality of multiplexers, for receiving arbiter control signals from the first storage processor and the second storage processor and transmitting multiplexer control signals to each of the number N of the plurality of multiplexers; and a midplane device coupled between the plurality of multiplexers and the data storage array for transferring the data signals from the plurality of multiplexers to the data storage array. The first storage processor, the second storage processor, the plurality of multiplexers, the plurality of arbiters and the midplane are all mounted on a single printed circuit board.

Single printed circuit board configuration for a data storage system

A data storage system has a chassis and a pair of printed circuit boards disposed in the chassis. Each one of the pair of printed circuit boards has disposed thereon a processor, a translator controlled by the processor, a SAS expander having a bidirectional front end port and multiple bidirectional backend ports, and an expansion port, and a SAS controller coupled between the translator and the expander. The system also has an interposer printed circuit board disposed in the chassis, and multiple multiplexers disposed on the interposer printed circuit board. Each one of the multiplexers has a pair of bidirectional front end ports and a pair of bidirectional back end ports. A first one of the pair of bidirectional front end ports is connected to a corresponding backend port of the SAS expander disposed on a first one of the pair of storage processor printed circuit boards. A second one of the pair of bidirectional front end ports is connected to a corresponding backend port of the SAS expander disposed on a second one of the pair of storage processor printed circuit boards. The system also has multiple disk drives disposed in the chassis. Each one is coupled to at least one backend port of a corresponding one of the multiplexers.

RAID data storage system with SAS expansion

A data storage system has a circuit board module, a set of Serial ATA devices, and a set of Serial ATA cables connecting the circuit board module to the set of Serial ATA devices. The circuit board module includes a circuit board, multiple host circuits mounted to the circuit board and multiplexer circuitry mounted to the circuit board. Each host circuit is configured to perform data storage operations on the behalf of an external client. The multiplexer circuitry is configured to (i) receive control signals from the host circuits and (ii) provide communications pathways between the host circuits and the set of Serial ATA devices in response to the control signals. Such an embodiment alleviates the need for multiple versions of disk drive assemblies and their associated costs.

Data storage techniques utilizing host-side multiplexers

A data storage system having a first chassis, such first chassis having a pair of SAS expanders and a second chassis having a pair of SAS expanders. The first one of the pair of SAS expanders is connected to only an expansion port of a first one of a pair of signal processor printed circuit boards in the first one of the chassis. An expansion port of a second one of the pair of SAS expander is connected to only the expansion port of a second one of the pair of signal processor printed circuit boards in the second one of the chassis.

SAS expansion topology for RAID data storage including multiplexers and SAS expanders for interfacing with single or dual ports drives

A data storage system includes a disk drive array including a plurality of disk drives; a first storage processor for controlling the operation of the data storage system; a second storage processor for controlling the operation of the data storage system; a first arbiter for controlling communication of data from the first storage processor and the second storage processor to a first group of disk drives of the disk drive array; and a second arbiter for controlling communication of data from the first storage processor and the second storage processor to a second group of disk drives of the disk drive array. Selected data is redundantly stored on disk drives in the first group of disk drives and the second group of disk drives, such that, upon failure of the first arbiter, the selected data is available to the first storage processor and the second storage processor through the second arbiter.

High availability data storage system

Disk drive spin-up is staggered to reduce peak power requirements. Spin-up of the drives is controlled by selectively delaying voltage inputs to the disk drives. Alternately, spin-up of the drives is controlled by staggering the timing of communications to the disk drives.

Disk drive input sequencing for staggered drive spin-up

Data storage equipment includes a first storage processor comprising a processing circuit and a collection of packaged integrated circuit devices which has a first set of ports and a second set of ports; a second storage processor; and an interconnect coupled between the first and second storage processors. The processing circuit of the first storage processor is adapted to execute as follows. The collection of packaged integrated circuit devices of the first storage processor is configured to provide (i) communications to a set of storage devices through the first set of ports of the collection of packaged integrated circuit devices and (ii) other communications to the second storage processor through the second set of ports of the collection of packaged integrated circuit devices. Communications is passed between the first storage processor and the set of storage devices through the first set of ports of the collection of packaged integrated circuit devices. Communications is passed between the first storage processor and the second storage processor through the second set of ports of the collection of packaged integrated circuit devices.

Managing serial attached small computer systems interface communications

An improved data storage system has a set of storage devices, a first storage processor and a second storage processor for storing data into and retrieving data from the set of storage devices. The first storage processor includes a processing circuit and a packaged IC device which has a first set of ports and a second set of ports. The processing circuit is adapted to configure the packaged IC device to provide (i) communications to the set of storage devices through the first set of ports and (ii) other communications to the second storage processor through the second set of ports. The processing circuit is further adapted to pass communications between the first storage processor and the set of storage devices through the first set of ports; and pass communications between the first storage processor and the second storage processor through the second set of ports.

Techniques for providing communications in a data storage system using a single IC for both storage device communications and peer-to-peer communications

A data storage system has a first storage processor, a second storage processor, and a communications subsystem. The communications subsystem has (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a clock circuit coupled to the interfacing portion, and (iii) a controller coupled to the interfacing portion and the clock circuit. The controller is configured to enable operation of the interfacing portion to provide communications between the first and second storage processors, sense a failure within the clock circuit, and reset the interfacing portion in response to the sensed failure to enable one of the first and second storage processors to continue operation. Such resetting of the interfacing portion prevents the remaining storage processor from locking up, thus freeing that storage processor so that it is capable of continuing to operate even after the failure.

Growing community of inventors

East Sandwich, MA, United States of America

John Victor Burroughs