Northrop Grumman Systems Corporation

Nanocrystal Imaging Corporation

Other

John V Veliadis

Ty Richard McNutt

Narsingh Bahadur Singh

Eric Jonathan Stewart

Andre E Berghmans

Brian Paul Wagner

Bettina A Nechay

David A Kahler

Li-shu Chen

David J Knuteson

Marc Eisenzweig Sherwin

Megan J Snook

Rameshwar N Bhargava

Nikhil R Taskar

Vishal Chhabra

Megan Jean McCoy

Stephen Van Campen

John Vincent Reichl

Neeta Pandit

Roger Delano

Harold C Heame, Iii

Bharail Kulkarni

An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.

Nano avalanche photodiode architecture for photon detection

A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.

Monolithic bi-directional current conducting device and method of making the same

A system/method for providing an optically triggered circuit breaker is provided. The system comprises a junction field-effect transistor (JFET) and gate drive coupled to the JFET's gate. The gate drive applies voltage bias (V) to the gate and the gate drive is configured to bias Vso that the system allows current flow through the JFET in the Drain to Source or Source to Drain directions, or so that the system blocks voltages applied to the Drain and/or Source. The system also comprises a photodetector which detects light emitted by the JFET resulting from a fault condition. The photodetector transmits a signal to the gate drive to provide the selectively biased Vso that the system blocks voltages applied to the Drain and/or Source, in response to the light detection. A system/method for providing an optically triggered bidirectional circuit breaker comprising common source JFETs and two photodetectors is alternatively provided.

System and method for providing optically triggered circuit breaker

A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.

Semiconductor devices with minimized current flow differences and methods of same

Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.

Bipolar junction transistor guard ring structures and method of fabricating thereof

A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first layer. The second layer has a dopant concentration that is higher than the dopant concentration of the first layer. The gates and the guard rings are formed simultaneously using a single mask.

Guard ring structures and method of fabricating thereof

A system and method for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. Embodiments include a first vertical-channel junction gate field-effect transistor (VJFET), a second VJFET, a gate drive coupled to the first VJFET gate and the second VJFET gate. Both VJFETs include a gate, drain (Dand D), and a source, and have gate-to-drain and gate-to-source built-in potentials. The first VJFET and the second VJFET are connected back-to-back in series so that the sources of each are shorted together at a common point S. The gate drive applies an equal voltage bias (V) to both the gates. The gate drive is configured to selectively bias Vso that current flows through the VJFETs in the Dto Ddirection, flows through the VJFETs in the Dto Ddirection or voltages applied to Dof the first VJFET or Dof the second VJFET are blocked.

System and method for providing symmetric, efficient bi-directional power flow and power conditioning

Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method that includes depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a single lithography step to pattern a mask over the interconnect metallization material, etching the interconnect metallization material in non-masked areas, and removing the stop-etch layer. A system comprises a stop-etch layer material for deposit into a stop-etch layer over a wafer, an interconnect metallization material for deposit over the chrome layer, a lithography operation for patterning a mask over the interconnect metallization material, a first etching compound for etching the interconnect metallization material, where the etching stops at the stop-etch layer, and a second etching compound for removing the stop-etch layer.

Systems and methods for interconnect metallization using a stop-etch layer

Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.

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Raleigh, NC, United States of America

John V Veliadis