Lsi Logic Corporation

Lsi Corporation

Symbios, Inc.

John V Sherman

Bret S Weber

Donald Roman Humlicek

Mohamad H El-Batal

Rodney A Dekoning

Keith W Holt

Charles E Nichols

Jason M Stuhlsatz

Timothy R Snider

Dale L Harris

A method for offloading a cache memory is disclosed. The method generally includes the steps of (A) reading all of a plurality of cache lines from the cache memory in response to an assertion of a signal to offload of the cache memory, (B) generating a plurality of blocks by dividing the cache lines in accordance with a RAID configuration and (C) writing the blocks among a plurality of nonvolatile memories in the RAID configuration, wherein each of the nonvolatile memories has a write bandwidth less than a read bandwidth of the cache memory.

System for optimizing the performance and reliability of a storage controller cache offload circuit

The present invention is directed to an apparatus capable of dual porting a serial advanced technology attachment (SATA) disk drive in a fault tolerant communication system, such as fiber channel. The dual porting apparatus includes two idle regenerators coupled to two serial master devices, a synchronization logic capable of synchronizing the communications between one of the idle regenerators and a third idle regenerator coupled to the SATA disk drive. Furthermore the dual porting apparatus may include an auto detector capable of enabling either of the first two idle regenerators, thus effectively switching between the two.

Dual porting serial advanced technology attachment disk drives for fault tolerant applications

Methods and associated apparatus for automatically synchronizing the operating code between a plurality of controllers. In a first embodiment after the spare controller is swapped into the storage subsystem, if the native controller determines that the spare controller's operating code is incompatible with the native controller's operating code, then the native controller notifies the spare controller that synchronization is required between both controllers. The native controller creates an image of its operating code including configuration parameters, and copies this 'synch info' into a reserved area of cache memory. The spare controller's main CPU utilizes mirroring routines to copy the operating code and configuration parameters into a reserved area of its cache memory. After the transfer is complete, the spare controller's main CPU loads the operating code and configuration parameters into its program memory and resets itself to operate with the modified program memory. In a second embodiment, a co-processor within the spare controller updates the spare controller's operating code by executing a script. The native controller builds the script that includes the operating code, configuration parameters, and instructions to retrieve the operating code and configuration parameters from the native controller's cache memory. The spare controller's co-processor transfers the script to a reserved area in the spare controller's cache memory. The native controller requests the spare controller's co-processor to execute the script which causes the co-processor to retrieve the operating code using mirroring techniques and load the spare controller's program memory with the operating code. The co-processor sends an interrupt to the spare controller's main processor to reset the spare controller.

Method and apparatus for synchronization of code in redundant

An arrangement of mounting pads on a substrate having segments, at least one of which has a plurality of mounting pads in a first row. Mounting pads of the first row are in connection with a corresponding offset through-hole oriented outwardly in the same general direction as a bisector definable for that segment, or oriented outwardly in the same general direction as a diagonal of the arrangement's outer shape. The segment defined can have a second and third row of mounting pads. The arrangement could include second, third, fourth, and so on, segments each with a plurality of mounting pads. Also included is an arrangement of Ball Grid Array (BGA) mounting pads on a circuit board for connection with electrical contacts of a BGA package, having: a first segment of a plurality of mounting pads in a first row with each mounting pad of the first row in connection with an offset through-hole oriented outwardly in the same general direction as a bisector definable for that first segment. More segments may be desired to accommodate a BGA package with a large number of leads. Additionally included, is a layer of a multi-layer circuit board having an arrangement of conductively-lined through-holes for electrical connection between layers. This arrangement has a first and second segment, each having a plurality of generally parallel rows of through-holes; the spacing between these two segments being generally greater than that between adjacent rows within either segment. The conductive lining of each through-hole is in connection with a mounting pad located on an outer side of the layer. Each through-hole is offset in an outwardly direction from its interconnected mounting pad.

Arrangement of pads and through-holes for semiconductor packages

Growing community of inventors

Derby, KS, United States of America

John V Sherman