Texas Instruments Corporation

Other

John V Schabowski

Karl M Guttag

Derek Roskell

Brian Shore

Kevin C McDonough

Thomas Preston

Marvin C Conrad

John Hayn, Ii

Jim A Carey

A method for detecting steps taken by a person in locomotion on foot having a step-detection apparatus carried on the person. The step-detection apparatus generates a signal in response to locomotion of the person. The signal is compared to the timing characteristics of human gait to identify steps taken. The step-detection apparatus can be carried in a front pants pocket of the person.

Pedometer method and apparatus

A digital processor system includes a processor, a memory and a memory interface between the processor and the memory. The memory stores data in one bit format but addresses the data in a second bit format. The interface to the memory includes a controller that is responsive to the processor, an information bus for the transfer of addresses and data and two registers to store addresses for the memory. These registers in the interface are responsive to the processor through the interface controls in order to allow the processor to increment or decrement the memory addresses or load new memory addresses from the information bus. These registers are then connected to a switch which is in turn responsive to the processor through the interface control in order that the processor can determine which register is to provide the address to the memory.

Quadruply extended time multiplexed information bus for reducing the

A digital processor system that includes a processor interface to an external memory. The interface to the external memory includes an information transfer bus to transfer information between the processor and the external memory and control circuitry to regulate the information on the information bus. This control circuitry includes the capability to delay the reading of information on the memory in order to allow for memory accesses to a slow memory. This delay capability is a selectable feature that is selected upon initialization of the processor.

Memory interface with automatic delay state

A digital synchronizer circuit including an input to receive an asynchronous level and a second input to receive an ansynchronous pulse. Both inputs are connected to the synchronizer input circuitry which will provide a level output for either type of input signal. This circuitry is connected to the remainder of the digital synchronizer which includes a latch connected to the level input and a level sensitive circuit connected to the output of the latch. The latch is constructed to provide a rapid transition between a logic '0' and '1'. In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from a logic '0' to a logic '1' when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit. The second latch is a two inverter latch with refresh for a three quarter of a machine cycle to allow any transient conditions within the latch to dampen out.

Synchronizer circuit with dual input

A digital processing system includes an external memory for the storage of program instructions for use with a separate processor that internally contains a memory for temporary storage, an arithmetic and logic means, a register set, control and timing circuitry, and two sets of data paths. The first set of data paths provide access to the external memory for transfer of instructions from the external memory to the processing unit. The second set of data paths provide for the internal routing of instructions data and addresses within the processor unit itself. The data structure for the first set of data paths is different than that for the second set of data paths, providing for an external data structure that is different than the internal data structure of the processor.

Single chip processor connected to an external memory chip

A quadruply time-multiplexed bus for digital processor systems. The quadruply time-multiplexed information bus is interfaced to a processor and an external memory to transfer addresses, data and program instructions between the processor and the external memory. The interface at the external memory includes the capability to store the addresses of extended bus or instructions being accessed. These stored addresses may be modified from the processor by the processor transmitting new addresses over the information bus or by having the processor activate selected control signals in the information bus interface which causes the stored address to be modified in response to the control signals. This feature is useful to read a new instruction from external memory without the requirement of a new transmission of program instruction address every time a new instruction is fetched by the processor.

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Houston, TX, United States of America

John V Schabowski