Zilog, Inc.

John Tran

Mazin Khurshid

Niraj Kumar

A clock signal generator for creating an output clock signal with fifty percent duty cycle and multiple of the input clock signal frequency allows generation of such a signal independent of input signal frequency and duty cycle. The generator utilizes an adjustable-delay oscillating feedback loop. A serial array of propagating delay elements measure the period of the input clock signal by triggering on successive input clock signal leading edges. This propagation lengthens the oscillating feedback loop until the output signal matches the desired frequency multiple. The feedback loop automatically adjusts according to a predetermined fraction of the period of the input clock signal. A fixed ratio of feedback loop delay to serial array delay ensures an output signal with a desired frequency multiple of the input signal frequency. Incorporation of an inverting logic gate in the oscillating feedback loop ensures a half-wave output clock signal having a fifty percent duty cycle.

Frequency multiplying clock signal generator

A control circuit suitable for generating control signals for controlling the bit and select lines for a static RAM and also for use in a buffer for reducing transient current and for controlling the slew rate. The circuit comprises a pull up and a pull down transistor, each having a first and a second terminal, and a passing gate connecting the second terminals of the two transistors. The gates of the two transistors are controlled by a signal. A first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and the second control signal at a second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal. When the control circuit is used for controlling a static RAM, the passing gate is always turned on. The two control signals are then used to control the bit and select lines of the static RAM. When a control signal is used in a buffer comprising a pull up and a pull down transistor, the input signal to the buffer is applied to the gate of the transistors ind the control circuit. The two control signals are applied to the gates of the pull up and pull down transistors of the buffer to reduce transient current.

Control circuit having outputs with differing rise and fall times

Initial data and/or control bits of registers within a digital integrated circuit are simultaneously loaded from localized non-volatile memory cells provided as part of the circuit. Such loading is accomplished each time the circuit is initialized, such as when power is first turned on to a system in which the circuit is a part. An important use of this technique is with a computer peripheral circuit chip such as a serial communications controller.

IC chip having volatile memory cells simultaneously loaded with

A control circuit suitable for generating control signals for controlling the bit and select lines for a static RAM and also for use in a buffer for reducing transient current and for controlling the slew rate. The circuit comprises a pull up and a pull down transistor, each having a first and a second terminal, and a passing gate connecting the second terminals of the two transistors. The gates of the two transistors are controlled by a signal. A first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and the second control signal at a second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal. When the control circuit is used for controlling a static RAM, the passing gate is always turned on. The two control signals are then used to control the bit and select lines of the static RAM. When a control signal is used in a buffer comprising a pull up and a pull down transistor, the input signal to the buffer is applied to the gate of the transistors in the control circuit. The two control signals are applied to the gates of the pull up and pull down transistors of the buffer to reduce transient current. In a further improvement, where the buffer includes a second inverter including a second pull up and a second pull down transistor, two feedback paths are employed to control the gates of the two transistors in the second inverter to control the slew rate of the buffer. The passing gate of the control circuit may be turned on or off by an enabling circuit so that if the circuit is implemented in an integrated circuit having input and output pins, the control circuit can be tri-stated so that an output pin may be used as an input pin when the passing gate is disabled.

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Sunnyvale, CA, United States of America

John Tran