Asm IP Holding B.v.

Arizona State University

Applied Materials, Inc.

Asm IP Holdings B.v.

Arizona Board of Regents, a Body Corporate

Other

John Tolle

Joe Margetis

John Kouvetakis

Eric R Hill

Matthew G Goodman

Nupur Bhargava

Robert Michael Vyne

Ignatius S T Tsong

David Kohen

Thomas Kirschenheiter

Matthew Bauer

Joseph P Margetis

Ellie Y Yieh

Jereld Lee Winkler

Zuoming Zhu

Junwei Su

Radek Roucka

Gregory Michael Bartlett

Jose Menendez

Sonti Sreeram

Cole J Ritter

Anchuan Wang

Mehul B Naik

Arvind A Kumar

Qi Xie

Mahendra Pakala

Keith Doran Weeks

Shu-Kwan Danny Lau

Patricia M Liu

Seshadri Ramaswami

Lori D Washington

Zhepeng Cong

Martin Jeffrey Salinas

Tomohiko Kitajima

Zihui Li

Ala Moradian

Gill Yong Lee

Dean Samara-Rubio

Saurabh Chopra

Ling Liao

Rami Khazaka

Lucas Petersen Barbosa Lima

Chia Cheng Chin

Manjunath Subbanna

Xinning Luan

Andrew Cockburn

Vanessa Pena

Changwu Hu

Shawn Thomas

Ignatius S Tsong

Abdul Wahab Mohammed

Gregory Deye

Matthew Gabriel Goodman

Shiva Rajavelu

Rich McCartney

Wei Hong

Daniel Philippe Cellier

Vijay D'Costa

Sandeep Mehta

Chang Wu Hu

Candi Cook

Levi Torrison

Three-dimensional dynamic random-access memory (3D DRAM) structures and methods of formation of same are provided herein. In some embodiments, a 3D DRAM stack can include alternating silicon (Si) layers and silicon germanium (SiGe) layers. Each of the Si layers may have a height greater than a height of each of the SiGe layers. Methods and systems for formation of such structures are further provided.

Reduced strain Si/SiGe heteroepitaxy stacks for 3D DRAM

A susceptor for processing a substrate is provided including a base and a coating formed over the base. The base includes an outer rim having an inner edge, an outer edge, and a top connecting the inner edge to the outer edge; and an inner dish disposed inside the outer rim and coupled to the outer rim, the inner dish recessed from the top of the outer rim, the inner dish having a front side and an opposing back side. The coating has an outer surface that includes a first portion formed over the front side of the inner dish. The first portion of the outer surface of the coating includes a first region and a second region, the first region has a first average level of roughness, the second region has a second average level of roughness.

Susceptor improvement

The present disclosure relates to flow guide structures and heat shield structures, and related methods, for deposition uniformity and process adjustability. In one implementation, an apparatus for substrate processing includes a chamber body that includes a processing volume. The apparatus includes one or more heat sources. The apparatus includes a flow guide structure positioned in the processing volume. The flow guide structure includes one or more first flow dividers that divide the processing volume into a plurality of flow levels, and one or more second flow dividers oriented to intersect the one or more first flow dividers and divide each flow level of the plurality of flow levels into a plurality of flow sections. The flow guide structure includes one or more third flow dividers oriented to intersect the one or more second flow dividers and divide the plurality of flow sections into a plurality of flow zones.

Flow guide structures and heat shield structures, and related methods, for deposition uniformity and process adjustability

Methods and devices for epitaxially growing boron- and gallium-doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

Method for depositing boron and gallium containing silicon germanium layers

A method for depositing a Group IV semiconductor is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include, exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA metalorganic dopant precursor. The methods may further include depositing a Group IV semiconductor on a surface of the substrate. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.

Method for depositing a Group IV semiconductor and related semiconductor device structures

Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Monolithic complementary field-effect transistors having carbon-doped release layers

A method of cleaning an epitaxial reaction chamber in-situ is disclosed. The method may include a pre-coating step, a high temperature baking step, and a gas etching step. The method is able to remove residue buildup within the reaction chamber, which may be made of quartz.

Method for cleaning quartz epitaxial chambers

Gas-phase reactor systems and methods suitable for use with precursors that are solid phase at room temperature and pressure are disclosed. The systems and methods as described herein can be used to, for example, form amorphous, polycrystalline, or epitaxial layers (e.g., one or more doped semiconductor layers) on a surface of a substrate.

Gas-phase reactor system-with a reaction chamber, a solid precursor source vessel, a gas distribution system, and a flange assembly

A semiconductor processing apparatus is disclosed that may include a reaction chamber joined by an upstream inlet flange and a downstream outlet flange wherein a longitudinal direction of the chamber extends from the inlet flange to the outlet flange and a plurality of ribs are provided on an outer surface of at least an upper chamber wall. The semiconductor processing apparatus may also include at least one array of heating elements disposed above the reaction chamber and at least one variable positioning device coupled to the at least one array of heating elements and configured to controllably adjust the position of the at least one array of heating elements relative to the position of the plurality of ribs.

Semiconductor processing apparatus and methods for calibrating a semiconductor processing apparatus

A method for forming a layer on a substrate includes providing a substrate in a reactor of a semiconductor processing system, the reactor having a divider separating an upper chamber from a lower chamber and a substrate holder therein, the substrate having upper and lower surfaces. The wafer is positioned within the reactor using the substrate holder such that the upper surface bounds the upper chamber, a silicon-containing gas is flowed through the upper chamber to deposit a layer of the upper surface, and a halogen-containing gas is flowed through the lower chamber to etch a deposited film on at least one wall bounding the lower chamber while flowing the silicon-containing gas through the upper chamber. Semiconductor processing systems are also described.

Method and device for depositing silicon onto substrates

Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

Three-color 3D DRAM stack and methods of making

A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation

Method for depositing a group IV semiconductor and related semiconductor device structures

A system for removing an oxide material from a surface of a substrate can include a substrate tray to receive the substrate, and a cooling body to receive the substrate tray. The system may include a first temperature control element configured to control a temperature of the substrate tray and a second temperature control element configured to control a temperature of the cooling body, where the first temperature control element and the second temperature control element can be independently controlled. A method for removing oxide material from a surface of a substrate can include providing the substrate on a substrate tray having heating elements, cooling the substrate by transferring heat from the substrate tray to a cooling body, depositing a halogen-containing material on the cooled substrate while the substrate is on the cooling body, and subsequently sublimating the halogen-containing material by heating the cooled substrate by transferring heat from the substrate tray to the substrate.

Pre-clean chamber and process with substrate tray for changing substrate temperature

Growing community of inventors

Gilbert, AZ, United States of America

John Tolle