International Business Machines Corporation

John Timothy Robinson

Peter Anthony Franaszek

Vittorio R Castelli

Caroline Benveniste

Charles Otto Schulz

Philip Heidelberger

Xiaowei Shen

Joy Aloysius Thomas

John Joseph Turek

Michael Edward Wazlowski

Zhigang Hu

Richard Orville LaMaire

Alexander Thomasian

Ioannis Kontoyiannis

Alper Buyuktosunoglu

Balaram Sinharoy

Chung-Sheng Li

Vijayalakshmi Srinivasan

Murthy V Devarakonda

Robert Brett Tremaine

Jude A Rivers

Lawrence David Bergman

William H Tetzlaff

Anant Deep Jhingran

Bernice E Rogowitz

Gerald P Bozman

John Alan Gerth

Joshua Wilson Knight, Iii

A communication system for multiple users whereby an automatic indication of away status is prompted immediately upon a user's departure from the vicinity of a computer or other medium. In a preferred embodiment, this is accomplished, in an instant messaging environment, via a video camera arrangement whereby, upon there being a detection of a user's absence from the immediate vicinity, an automatic prompt is made to indicate away status for the user.

Computer-based communication systems and arrangements associated therewith for indicating user status

A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.

Cost-conscious pre-emptive cache line displacement and relocation mechanisms

Embodiments of a method for reducing conflict misses in a set-associative cache by mapping each memory address to a primary set and at least one overflow set are described. If a conflict miss occurs within the primary set, a cache line from the primary set is selected for replacement. However, rather than removing the selected cache line from the cache completely, the selected cache line may instead be relocated to the overflow set. The selected cache line replaces a cache line in the overflow set, if it is determined that the selected cache line from the primary set has an estimated age that is more recent than an estimated age for any cache line in the overflow set. Embodiments of the method incorporate various techniques for estimating the age of cache lines, and, particularly, for estimating the relative time since any given cache line was last accessed.

Set-associative cache using cache line decay counts and set overflow

A method, apparatus and computer product wherein means and mechanisms are provided whereby, in a distributed or clustered shared file system, (1) concurrency classes may be defined specifying granularity of locking, whether locks are cached, and whether modified data is written-through at the completion of updates, (2) certain files, file types, or files and/or file types as used by given applications or classes of applications, may be associated with concurrency classes, and (3) for each usage of a file by an application, the associated concurrency class determines a policy for choosing specific concurrency and coherency control mechanisms to be used for accessing the given file.

Concurrency classes for shared file systems

Arrangements and method for enabling and disabling cache bypass in a computer system with a cache hierarchy. Cache bypass status is identified with respect to at least one cache line. A cache line identified as cache bypass enabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is bypassed, while a cache line identified as cache bypass disabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is not bypassed. Included is an arrangement for selectively enabling or disabling cache bypass with respect to at least one cache line based on historical cache access information.

Enabling and disabling cache bypass using predicted cache line usage

A method and structure is disclosed for constraining cache line replacement that processes a cache miss in a computer system. The invention contains a K-way set associative cache that selects lines in the cache for replacement. The invention constrains the selecting process so that only a predetermined subset of each set of cache lines is selected for replacement. The subset has at least a single cache line and the set size is at least two cache lines. The invention may further select between at least two cache lines based upon which of the cache lines was accessed least recently. A selective enablement of the constraining process is based on a free space memory condition of a memory associated with the cache memory. The invention may further constrain cache line replacement based upon whether the cache miss is from a non-local node in a nonuniform-memory-access system. The invention may also process cache writes so that a predetermined subset of each set is known to be in an unmodified state.

Cache configuration for compressed memory systems

In a computer system in which a plurality of hosts is connected through an interconnection network, an apparatus coupled to the interconnection network for allowing the plurality of hosts to share a collection of memory sectors, the memory sectors storing compressed data, is provided. The apparatus includes a network adapter for coupling the apparatus to the interconnection network; a memory for storing the collection of memory sectors; and control logic for managing the memory, the control logic including a memory compressor/decompressor. The memory further includes a directory for translating real addresses of at least one host to an address in the apparatus. A method for managing a number of memory sectors used by each host and a method for translating a real address specified by at least one host into a real address of the apparatus is also provided.

Direct addressed shared compressed memory system

A method and structure for replacing cache lines in a computer system having a set associative cache memory is disclosed. The method establishes ranking guidelines utilizing a writable cache replacement control array, wherein the guidelines can be dynamically changed by writing data to the cache replacement control array. The invention ranks states of different cache lines according to the ranking guidelines and replaces, upon a cache miss, a cache line having a highest rank of the rankings.

Reconfigurable cache controller for nonuniform memory access computer systems

A method for selecting a line to replace in an inclusive set-associative cache memory system which is based on a least recently used replacement policy but is enhanced to detect and give special treatment to the reloading of a line that has been recently cast out. A line which has been reloaded after having been recently cast out is assigned a special encoding which temporarily gives priority to the line in the cache so that it will not be selected for replacement in the usual least recently used replacement process. This method of line selection for replacement improves system performance by providing better hit rates in the cache hierarchy levels above, by ensuring that heavily used lines in the levels above are not aged out of the levels below due to lack of use.

Prioritizing and locking removed and subsequently reloaded cache lines

A compressed memory system includes a cache, and compressed memory including fixed size storage blocks for storing both compressed data segments and fixed size storage blocks defining a virtual uncompressed cache (VUC) for storing uncompressed data segments to enable reduced data access latency. The compressed memory system implements a system and method for controlling the size of the VUC so as to optimize system performance in a manner which permits the avoidance of operating system intervention which is required in certain circumstances for correct system operation. The system solves-these problems by implementing one or more thresholds, which may be set by the operating system, but which, after being sets control the size of the VUC independently of the operating system or other system software.

Virtual uncompressed cache size control in compressed memory systems

In a computer system having a processor, a memory system including multiple levels of caches L , L , . . . , L and including main memory L , and in which the cache L includes lines of size s and the cache L includes lines of size t with t>s, a dual line size cache directory mechanism, in which the contents of a cache L may be accessed at line size granularity s (in which case it is determined whether a line corresponding to a given memory address is stored in L , and if so its location and status), and in which the contents of L may also be accessed at line size granularity t (in which case it is determined whether any of the t/s lines of size s residing in the larger line of size t corresponding to a given memory address are stored in L , and if so their locations and status) without multiple sequential accesses to a cache L directory structure.

Dual line size cache directory

A computing system includes a storage server having a memory organization that includes a compressed memory device for storing sectors, each sector having a sector data portion and associated header and trailers, either attached by the hosts or by components of the computing system. The compressed memory device comprises a memory directory and a plurality of fixed-size blocks. The system implements a methodology for detaching headers and trailers from sectors before storing the sectors in the memory, and storing the headers and trailers in the memory disk cache, separate from the sector data portion; and, reattaching headers and trailers to sector data portions when the sectors are sent from the memory to a host or to a mass storage device. The header and trailer data are managed through the same memory directory used to manage the compressed main memory. The process of detaching headers and trailers from sectors for separate storage results in increased efficacy of data compression, thus yielding better compression ratios, and decreased memory traffic generated by host reads, host writes, cache stages and cache destages.

System and method for storing data sectors with header and trailer information in a disk cache supporting memory compression

A computerized method, system and computer program product for managing an object store is disclosed. An exemplary method includes the the steps of: collecting performance statistics about storage repositories from which an object(s) can be retrieved; retrieving an object from a storage repository, in response to an object reference; determining a reference probability (RFP) for the object; determining and associating a replacement penalty (RPP) with the object wherein the RPP is based on the one or more performance statistics and the RFP; and storing the object and an associated RPP for the object. The storage repositories could be locally attached devices, network sites, and/or remotely attached devices. If there is insufficient space in the object store for a new object, an object(s) can be replaced with the new object based on the associated RPP of the cached objects. Alternatively, the resolution of one or more objects in the object store can be reduced until sufficient space is available. The RPP determination is preferably based on the RFP for the object and performance and/or usage statistics. Examples of the performance statistics include: availability; size; latency; and bandwidth. An example of the usage statistics includes statistics on time delays (D) associated with abort requests made via the Internet, for example, using a browser. The RPP could include an annoyance function for a specific requester or set of requesters by instrumenting the browser STOP function and analyzing time interval statistics associated with its usage.

Managing an object store based on object replacement penalties and reference probabilities

The memory space (often in the form of cache) in a system (e.g., an Internet proxy or web browser) is conserved by saving low resolution versions of data objects when the full resolution version is removed (e.g., due to age, using a least recently used (LRU) replacement policy) in order to create space for new objects. This provides for efficient use of the memory space. In many situations, the low resolution version of the data object is of adequate quality for usage. Further, even when this is not the case, it can be useful to quickly obtain a low resolution version and then with some delay, obtain the full resolution version at the user or application's request. Particular advantageous embodiments of methods, apparatus and article of manufacture implementing the invention are presented.

Conserving storage space by means of low resolution objects

A system including a CPU, memory, and compression controller hardware, and implementing a first directory structure included in a first memory wherein CPU generated real memory addresses are translated into one or more physical memory locations using the first directory structure, further includes a second directory cache structure having entries corresponding to directory entries included in the first directory structure. In a first embodiment, the second directory cache structure is implemented as part of compression controller hardware. In a second embodiment, a common directory and cache memory structure is provided for storing a subset of directory entries in the directory structure together with a subset of the memory contents.

Growing community of inventors

Yorktown Heights, NY, United States of America

John Timothy Robinson