Lucent Technologies Inc.

At&t Bell Laboratories

At+t Corp.

Bell Telephone Laboratories

Agere Systems Inc.

John Thomson, Jr

David Wilfred Johnson

Debra Anne Fleming

Apurba Roy

Sungho Jin

Gregory Peter Kochanski

Henry M O'Bryan, Jr

Vincent George Lambrecht, Jr

Gideon S Grader

David W Johnson, Jr

Henry Hon Law

Edwin Arthur Chandross

David A Norte

Henry Miles O'Bryan

Warren W Rhodes

Karl Georg Hampel

Wei Zhu

King Lien Tai

John Burnette MacChesney

Thomas H Tiefel

Robert Bruce Van Dover

James Kevin Plourde

Eliezer M Rabinovich

James W Fleming, Jr

George E Peterson

Gideon Grader

Roderick Kent Watts

Te-Sung Wu

Randall F Bell

David Joseph Liptack

James Kevin Pluorde

A ferrite layer formation process that may be performed at a lower temperature than conventional ferrite formation processes. The formation process may produce highly anisotropic structures. A ferrite layer is deposited on a substrate while the substrate is exposed to a magnetic field. An intermediate layer may be positioned between the substrate and the ferrite to promote bonding of the ferrite to the substrate. The process may be performed at temperatures less than 300&deg; C. Ferrite film anisotropy may be achieved by embodiments of the invention in the range of about 1000 dyn-cm/cm to about 2&times;10 dyn-cm/cm .

Ferrite film formation method

An antenna structure including at least one planar antenna element. In place of a balun, the antenna structure further includes a slotline for coupling the planar antenna element with an unbalanced load.

Broadband antenna structure

The specification describes a phase shifting microstrip device in which the ground plane electrode is formed on a substrate surface and a film of ferroelectric material with a thickness less than 200 &mgr;m is formed over the ground plane electrode. The microstrip electrode is formed over the film of ferroelectric material to produce a microstrip device with an operating voltage of less than 200 volts.

Microstrip phase shifters

The invention provides an improved process for fabricating devices containing metallized magnetic ceramic material, such as inductors, transformers, and magnetic substrates. In particular, the unique vias utilized in the process of the invention allow fabrication of devices from multiple unfired ferrite layers with only a single via-coating step, thereby avoiding the need numerous punching steps. Moreover, there is no need for expanding the dimensions of the vias and thus no need for internal metallization. The invention therefore provides for green tape-type fabrication of devices such as inductors, transformers, and magnetic substrates in a manner faster, less complex, and more reliable than current methods. The invention also relates to use of an improved conductive material in such a process, the conductive material containing silver/palladium particles, ferrite particles, a cellulose-based or other organic binder, and a solvent. After firing of the substrate onto which the ink has been coated, and plating of copper thereon by a copper pyrophosphate bath, the plated copper exhibits a pull strength greater than about 4 kpsi, advantageously greater than about 5 kpsi. Use of a copper pyrophosphate bath also allow uniform plating within long, narrow vias.

Process for forming device comprising metallized magnetic substrates

Cracking in thin sheets of sol-gel-produced material is avoided by use of a support liquid during gelation and drying. Silica glass, as well as other glass and ceramic bodies, is contemplated.

Fabrication including sol-gel float processing

An inductor (100) optimized for surface-mount vacuum-pickup automated circuit assembly eliminates the expense of an inductor housing. The inductor has a hollow rectangular ferrite core (101) and a winding defined by a stripline (102) deposited on the core surface. Winding ends are formed by conductive vias (103) in the core that open onto the core surface, where they connect and mount the inductor to a circuit board (150). A flat sheet (104) adhered to one face of the core provides a surface for vacuum pickup and for labeling of the inductor. The core of a passively tuneable inductor (200) defines multiple unconnected winding segments (102-103). Segment ends mount the inductor to the circuit board and connect the segments to circuit board striplines (254) that are laid out in a pattern to interconnect a number of the segments into a winding. The inductor is tuned by changing the stripline layout and thereby varying the number of interconnected segments. The core of an electromagnetic interference choke (300) defines two windings wound axially in parallel and radially in opposite directions. The core of a choke (500) that permits stacked mounting defines additional conductive vias (503) for connecting the windings of a second choke (300) mounted on the core to the circuit board. For electromagnetic isolation, the windings of the two chokes are oriented orthogonally to each other.

Stackable, passively-tunable, cost-reduced inductor

A transformer (FIG. 1) optimized for surface-mount vacuum-pickup automated circuit assembly eliminates the expense of a transformer housing. The transformer has a ferrite body (100) that defines a pair of wells (208, 209) each opening onto an opposite face (108, 109) of the ferrite body. Transformer primary and secondary windings are wound in a coil (103) through slots (210, 211) around a transformer core (204) at the bottom of the wells. The windings do not protrude from the wells beyond the faces, resulting in flat faces. A first plurality of conductive vias (104-106), one pair for each winding, are completely embedded in the ferrite body and extend to both of the faces. Each pair of vias serves at one face to attach to the winding and at the other face to attach to solder pods of a PC board. The embedded vias also serve as EMI filters. A plate (107) covers the one face and provides a surface for vacuum pickup and for labeling of the transformer. The ferrite body (500) of a first transformer (FIG. 5) adapted for stacked mounting of transformers dispenses with the flat plate and further defines a second plurality of pairs of conductive vias (104-106). These vias are not connected to the first transformer's windings, but rather are positioned for connection to the winding-connected first pairs of vias of a second transformer that is positioned orthogonally to and mounted on the first transformer at the one of the faces.

Stackable and cost-reduced transformer with embedded EMI filters

The method of making a metallized magnetic substrate for devices including a magnetic component involves providing an unfired ceramic body. In one exemplary embodiment, the method further involves making one or more vias through the ceramic body, coating the via side walls with conductive material, forming an aperture through the ceramic body, such that an aperture edge intersects the via, and metallizing the unfired ceramic body such that a conductive pathway is formed that includes the conductive material in the via. Finally, the metallized unfired ceramic body is fired in conventional fashion, optionally followed by deposition of additional conductor material.

Method of making a device including a metallized magnetic substrate

The present invention provides improved techniques for metallizing ceramic substrates. The method comprises providing a ceramic substrate and depositing a layer of reducible material on the ceramic substrate. The layer of reducible material includes a reducible ceramic such as copper oxide. The ceramic substrate having the layer of reducible material disposed thereon is heated and the reducible material is contacted with a reducing agent to create a conductive region. The conductive region is either a metallized region formed by reduction, or it is a conductive ceramic formed through surface reduction. The present invention further provides a metallized ceramic substrate. The metallized layer comprises ceramic regions having at least one constituent in common with the ceramic substrate. The ceramic substrate and the ceramic regions of the metallized layer are sintered to each other such that the metallized region is interspersed between the sintered ceramic regions. In this fashion, the metal is firmly held to the ceramic substrate due to the presence of the bonded ceramic within the metallized layer.

Metallization of ceramic through application of an adherent reducible

The pillar structure according to the invention has a substantially longer surface path length from negative to positive electrodes resist breakdown in a high voltage environment. The processing and assembly methods in this invention permit low-cost manufacturing of high breakdown-voltage, dielectric pillars for the flat panel display.

Method for making improved pillar structure for field emission devices

In accordance with the invention, a field emission device is made by disposing emitter material on an insulating substrate, applying a sacrificial film to the emitter material and forming over the sacrificial layer a conductive gate layer having a random distribution of apertures therein. In the preferred process, the gate is formed by applying masking particles to the sacrificial film, applying a conductive film over the masking particles and the sacrificial film and then removing the masking particles to reveal a random distribution of apertures. The sacrificial film is then removed. The apertures then extend to the emitter material. In a preferred embodiment, the sacrificial film contains dielectric spacer particles which remain after the film is removed to separate the emitter from the gate. The result is a novel and economical field emission device having numerous randomly distributed emission apertures which can be used to make low cost flat panel displays.

Spaced-gate emission device and method for making same

The thickness uniformity of a plated metal layer inside a via hole can be enhanced by intersecting a conductive via with an insulating aperture before plating. The new via configuration improves the mass transfer of the plating. It is believed that the apertures lower the local solution ohmic resistance near the via holes. The method can be applied to the manufacture of a wide variety of circuit boards.

Method for fabricating highly conductive vias

The disclosed multi-pixel flat panel displays (e.g., flat panel field emission displays (FPFED) or liquid crystal displays (LCD)) includes spaced apart first and second electrodes, with a patterned solid material layer in contact with one of the electrodes, exemplarily between the two electrodes. The patterned layer (referred to as the 'web') includes a multiplicity of apertures, with at least one (preferably three or more) aperture associated with a given pixel. In the aperture is disposed a quantity of a second material, exemplarily, a phosphor in the case of an FPFED, or a color filter material in the case of a LCD. The web can facilitate second material deposition by means of, e.g., screen printing, typically making possible formation of smaller phosphor or filter dots than was possible by prior art device. The web also can facilitate provision of spacer structure between the two electrodes, and can include getter or hygroscopic material.

Growing community of inventors

Spring Lake, NJ, United States of America

John Thomson, Jr