Intel Corporation

John Thomas Sprietsma

Michael W Leddige

Kuljit Singh Bains

Lilly Huang

Henry W Koertzen

Steve Joy

Stephen S Pawlowski

Bryce D Horine

Jerzy B Kolinski

James V Noval

Julie Scheyer-Furnanz

Henry Schaechterle

A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.

Interchangeable connection arrays for double-sided DIMM placement

A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate.

A power supply system, a circuit board, and a computer, as well as a method of providing power to a circuit element are disclosed. The power supply system may include two or more voltage sources coupled to a circuit element. The voltage output of one voltage source may be coupled to one portion of a plurality of power and return connection terminals on the circuit element, and the voltage output of another voltage source may be coupled to another portion of the plurality of power and return connection terminals. The method may include selecting the portions of the power and return connection terminals, and connecting voltage sources to the selected portions.

Multiple return terminal power supply methods and apparatus

A circuit board assembly is provided, comprising a first circuit board and a ball-grid array jumper. The ball-grid array jumper comprises a second circuit board smaller in size than the first printed circuit board and has at least one layer of conductive traces and at least two solder ball connectors. The ball grid array jumper is mounted to the first printed circuit board via the solder ball connectors.

Ball grid array circuit board jumper

A circuit board includes electrical interconnect mounting pads for mounting electronic devices thereto. Some of the electrical interconnect mounting pads include a plated through hole which traverses through the circuit board. One end of the plated through holes is closed, plugged or covered to prevent migration of solder through the plated through holes during a solder operation. The reduction in solder migration, as a result of plugging the plated through hole, increases solder joint quality over solder joint quality achieved using plated through holes which are not closed at one end.

Apparatus and method for improving circuit board solder

A multi-layer printed circuit board includes power planes located on outer conductive layers. The outer conductive layers are patterned to accept circuitry, such as integrated circuits and surface mount devices. Mounting pads are provided on the outer conductive layers which include plated through vias for electrical interconnection with other conductive layers of the printed circuit board. To increase solderability, the plated through vias are located on the mounting pads such that they are covered by the circuit component mounted thereto. By locating the vias under the electrical components, such as surface mount capacitors, the quality of solder fillets is increased. To enhance heat dissipation, openings are provided in solder masks located on exterior surfaces of the outer conductive planes. These openings are located in the solder mask to expose the conductive plane. As such, the openings are located in areas where circuitry is not mounted to the printed circuit board.

Multiple layer printed circuit board having power planes on outer layers

Disclosed is a multilayer (e.g., 4-layer) printed circuit board and method of manufacture thereof. The multilayer printed circuit board has at least one inner substrate (inner core) that includes a phenolic resin (e.g., a phenolic resin-laminated paper). Outer insulating layers of the multilayer printed circuit board can have a low dielectric constant (e.g., 3.8-4.4) and a high T,(e.g., 180&deg;-200&deg; C.). The multilayer printed circuit board can be provided by steps including forming electrical circuit patterns from a copper foil on the inner substrate, to form a printed circuit board, forming a stack of at least one printed circuit board and outer copper foil layers, with insulating layers of, e.g., a semi-cured resin (e.g., prepreg layers) interposed between adjacent conductive metal layers, and then laminating the stack.

Multilayer printed circuit board and manufacturing method thereof

A connector for coupling high frequency signals between devices includes a substrate having an array of vias for coupling a reference voltage to reference voltage traces that extend along the substrate surface between the devices. Signal traces including device pads for coupling signals to and from the devices alternate with the reference voltage traces. The widths of the reference voltage traces are varied to maintain a substantially constant separation between the reference voltage trace and an adjacent signal trace.

Via pad geometry supporting uniform transmission line structures

An equal length symmetric computer bus topology. The equal length symmetric computer bus topology provides a bus signal path to a number of bus nodes. Each bus signal path extends from each node on the computer bus to a central junction point. The bus signal paths are of equal length and have identical electrical characteristics. The equal length symmetric computer bus topology minimizes the effect of transmission line reflections upon the bus signals. The equal length symmetric computer bus topology also causes very little clock skew.

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Portland, OR, United States of America

John Thomas Sprietsma