Intel Corporation

John Tang

Steven N Towle

Henning Braunisch

Daoqiang Lu

Yuan-Liang Li

Jiangqi He

Thomas Dory

Rajendran Nair

Gilroy J Vandentop

Dong Zhong

Jung S Kang

John S Cuendet

A semiconductor device is provided that includes one or more ceramic material layers and one or more low dielectric constant (low-K) epoxy layers on top to be electrically coupled to an integrated circuit device, such as a chip die. The resulting ceramic/organic hybrid substrate takes advantage of the thin low-cost, low-K epoxy layer, by routing the dense circuitry from the chip die to the ceramic material layer. In addition, the use of low-K epoxy layer may reduce the number of ceramic material layers required to about three layers, thus significantly reducing the cost of the substrate. Low-K epoxy material layer may be laminated onto the ceramic material layer to reduce throughput time and cost. The ceramic/organic hybrid substrate may also take advantage of the properties of ceramic materials, which have a much more rigid structure than organic materials and a low CTE (coefficient of thermal expansion) that works well with ultra low-K chip dies. The ceramic/organic hybrid substrate also may make possible the fabrication of a bottom cavity package for capacitors placement.

Ceramic/organic hybrid substrate

An embodiment of the present invention is a technique to fabricate a package. A metal sheet having trenches is formed. A thinned wafer supported by a wafer support substrate (WSS) is formed. The metal sheet is bonded to the WSS-supported thinned wafer to form a metal bonded thinned wafer. The thinned wafer is diced to the trenches into die assemblies.

Wafer-level bonding for mechanically reinforced ultra-thin die

A device comprises a substrate core having power paths through it and an input/output signal routing layer upon the core substrate. An integrated circuit may be arranged on the routing layer such that the integrated circuit is electrically coupled to the substrate core through the routing layer.

Decoupled signal-power substrate architecture

A low cost microelectronic circuit package includes a single build up metallization layer above a microelectronic die. At least one die is fixed within a package core using, for example, an encapsulation material. A single metallization layer is then built up over the die/core assembly. The metallization layer includes a number of landing pads having a pitch that allows the microelectronic device to be directly mounted to an external circuit board. In one embodiment, the metallization layer includes a number of signal landing pads within a peripheral region of the layer and at least one power landing pad and one ground landing pad toward a central region of the layer.

Low cost microelectronic circuit package

A low cost technique for packaging microelectronic circuit chips fixes a die within an opening in a package core. At least one metallic build up layer is then formed on the die/core assembly and a grid array interposer unit is laminated to the build up layer. The grid array interposer unit can then be mounted within an external circuit using any of a plurality of mounting technologies (e.g., ball grid array (BGA), land grid array (LGA), pin grid array (PGA), surface mount technology (SMT), and/or others). In one embodiment, a single build up layer is formed on the die/core assembly before lamination of the interposer.

High performance, low cost microelectronic circuit package with interposer

According to one aspect of the invention, a electronic assembly is provided. The electronic assembly includes a motherboard, a first microelectronic die on a package substrate, a second microelectronic die, and a strip of flex tape interconnecting the microelectronic dies. The package substrate has a metal core with via openings, power conductors connecting a top and bottom surface of the substrate and passing through the via openings, and ground conductors interconnecting the metal core with the top and bottom surface of the package substrate. The flex tape has signal conductors which interconnect the microelectronic dies. Power is provided to the first microelectronic die via the power conductors. IO signals are sent between the microelectronic dies over the signal conductors in the flex tape.

Growing community of inventors

Phoenix, AZ, United States of America

John Tang