Unisys Corporation

Cadence Design Systems, Inc.

Sperry Corporation

John T Rusterholz

James R Hamstra

Joseph P Kerzman

James Edward Rezek

Archie E Lahti

Charles J Homan

Larry L Byers

Donald B Bennett

Mark D Aubel

Michael Danilenko

Howard A Koehler

Richard F Paul

Louis B Bushard

David J Tanglin

Robert J Malnati

John R Schomburg

Lowell E Brown

Arthur F Boehm

A method and apparatus for distributing clock drivers within a hierarchical circuit design, wherein the clock drivers are concentrated in locations where they are actually needed rather than uniformly distributed throughout the circuit design. In an exemplary embodiment, the actual clock loads within a selected hierarchical region are determined, and a sufficient number of clock drivers are added as children objects to the selected hierarchical region. Since many placement tools may place the children objects within an outer boundary of the corresponding parent object, the clock drivers, as children objects of the selected hierarchical region, may be placed within the outer boundary of the selected hierarchical region. Accordingly, the clock drivers may be concentrated in the locations where actually needed.

Method and apparatus for distributing a clock tree within a hierarchical

A computer-based system and method for efficiently identifying a new index bit sequence, utilizing a single technique to rearrange any size table, generating new index bit sequences without utilizing a significant amount of memory resources, and rearranging table entries only once. A mask array defines the new index bit sequence for a new table. The mask array has N entries of N bits each where N is equal to the number of bits in the old table index. The table entries in the old table to form a new table by initializing an old table index (OI) and a new table index (NI) and setting the new table entry associated with the NI equal to the old table entry associated with the OI. Then the new index that is associated with the next old index value by using the mask array to sequentially mask bits in the NI corresponding to mask bits in the mask array is dynamically generated. Then the new table entry associated with the generated new table index value is assigned with the old table entry associated with the sequentially increased old table index. The process repeats for all values of the old index. The new table, once completed, is used in place of the old table. Accordingly, the system utilizes significantly less memory and operates more efficiently than conventional systems and methods.

System and method for reordering lookup table entries when table address

A computer-based system and method for efficiently identifying inverted bits in an address, utilizing a single technique to rearrange any size table, generating new index bit sequences based upon inverted index bits without utilizing a significant amount of memory resources, and rearranging table entries only once. The present invention utilizes a mask that defines the address bits that are inverted for a new table. The present invention then rearranges the table entries in the old table to form a new table. Once generated the new table can be used in place of the old table thereby requiring no more memory than the old table. Accordingly, the present invention provides a system and method for identifying the index bits to be inverted after the lookup table and computer program have been generated while utilizing significantly less memory than conventional systems and methods.

A method used by a computer-aided design system for placing logic functions and cells in a floor plan of a very large scale integrated circuit chip. The structure of a set of selected logic functions and cells to be placed is compared to a set of selected logic functions and cells which have previously been placed in the floor plan. If the number of cells and the structure of the sets are analogous, the selected logic functions and cells to be placed are automatically assigned physical positions in the floor plan based on the physical position and structure of the selected logic functions and cells that have already been placed, and on an orientation mode. The orientation mode provides for the reflection of the placement of the selected logic functions and cells about the horizontal axis, the vertical axis, or both the horizontal and vertical axes. The size of the sets of selected logic functions and cells may be arbitrarily large, thereby providing advantages over simple manual placement of logic functions and cells in a floor plan.

Method for placing logic functions and cells in a logic design using

A method used by a digital computer for generating a preferred processing order of the vertices in a directed graph. The method also detects any cycles that exist in the directed graph. The vertices of the directed graph represent components of a system and the arcs represent the interrelationships between components. Each arc is defined by a vertex pair consisting of a starting vertex and an ending vertex. Each vertex is either assigned or unassigned to a processing order and marked as either a leaf vertex or a non-leaf vertex. The method includes traversing the set of arcs of the directed graph and marking the starting vertex as a non-leaf vertex for each arc whose ending vertex is unassigned, traversing the set of vertices and for each vertex that is unassigned and a leaf vertex, assigning the vertex to the processing order; and for each vertex that is unassigned and a non-leaf vertex, marking it as a leaf vertex. If unassigned vertices remain in the set of vertices and no vertices were assigned to the processing order then a cycle exists in the directed graph. These steps are repeated as long as there are vertices in the set of vertices that are unassigned and no cycle has been detected.

Method for generating a preferred processing order and for detecting

A tightly coupled data processing system having high performance characteristics, including at least one general purpose host processor coupled to host processor ports of a High Performance Storage Unit, and a Scientific Processor directly coupled to scientific processor ports of the High Performance Storage Unit is described. The Scientific Processor is under task assignment control of the host processor and shares the same memory space as the host processor, and thereby provides the tight coupling without need of dedicated memory or caching. Provision is also made for the Scientific Processor to share the virtual address space of the host processor. A tightly coupled system is also disclosed wherein a plurality of general purpose host processors are each coupled to one or more High Performance Storage Units, and a Multiple Unit Adapter is utilized to couple an associated Scientific Processor to all of the High Performance Storage Units. Each Scientific Processor includes a parallel operable scalar processor module and a vector processor module.

Tightly coupled scientific processing system

An improved Scientific Processor for use in a data processing system having a general purpose host processor and a High Performance Storage Unit, and under operational control of the host processor is described. The Scientific Processor includes a Vector Processor Module and a Scalar Processor Module, each operable at comparable rates, wherein scalar operands and vector operands can be manipulated in various combinations under program control of an associated host processor, all without requirement of dedicated storage or caching. The Scalar Processor Module includes instruction flow control circuitry, loop control circuitry for controlling nested loops, and addressing circuitry for generating addresses to be referenced in the High Performance Storage Unit. A scalar processor arithmetic logic unit is described for performing scalar manipulations. The Vector Processor Module includes vector control circuitry and vector file storage circuitry together with vector file loading and vector storage circuitry. A plurality of vector manipulating pipelines for performing instruction functions of vector addition, vector multiplication and vector move is described wherein the pipelined functions can occur simultaneously, and each pipeline is capable of providing resultant operand pairs at a rate approximately equal to the reference cycle of the High Performance Storage Unit.

Scientific processor to support a host processor referencing common

A loop control mechanism is described for use in a vector-oriented scientific data processing system. Because of the vector-oriented nature of scientific programs used on digital data processing systems the efficient control of program loops is of major importance. It can be shown that a procedure coded as N nested DO loops in FORTRAN will generally require 2N-1 nested loops of scientific processor object code, given a vector register architecture. Except for the innermost level, it is necessary at each level to iterate by strips up to the vector length and within that vector length strip to iterate by elements. For the innermost loop, iteration by element is not needed, but is implicit in vector operations. The present mechanism accomplishes this loop control optimization by maintaining the parameters for loop control in separate loop control registers. The use of this special facility for these parameters provides for their efficient management. The novelty of this invention centers around having special registers and unique instructions dedicated to the handling of the loop parameters. The use of these special registers and instructions for the controlling of these loops make it possible to efficiently precompute loop-counts, thereby enhancing the speed of the scientific processor.

Loop control mechanism for scientific processor

A vector data reduction to a scalar result in which adjacent elements in the vector are paired and each pair is sequentially reduced in an arithmetic unit organized for so-called pipe line operation is described. The results of each paired pass are stored as result vector elements and these elements are similarly paired, sequentially operated upon, and stored as result vector elements. The process continues until there is but one pair left which is operated upon to produce a singular, scalar result.

Method and apparatus for performing a vector reduction

A local store for a scientific vector processor which provides high speed access to scalar variables, parameters, temporary operands, and register save area contents of the system. Basically, the local store is a general purpose storage structure which provides access which is as fast as access to the general or vector registers of the vector processor. It is capable of being accessed either directly or indirectly via indexing. It resides in the virtual address area of the machine so that it is accessible for either reading or writing by the host programs. Because of its positioning in relation to the high performance main storage unit its size is transparent to the other programs of the system since it overflows automatically into the main storage unit. It also has multiple interfaces which provide a more simple matching of the bank widths and transfer rates of the rest of the scientific processor.

Local store for scientific vector processor

A method and a means of increasing the performance of an instruction buffer in a digital data processing system is disclosed. The improvement is accomplished by by-passing the content addressable memory operation which has heretofore been utilized to access page addresses in the instruction buffer. As each word included on the same page was accessed, the CAM was repetitiously activated even though it was accessing the same page. In the present system, word accesses made to the same page are handled in a much improved manner. In the present system, a comparator is implemented in the system which compares the presently reference page with the previously referenced word, so that when a match is noted, i.e., the same page is indicated, the CAM is bypassed and successive requests made to the same page are satisfied from the instruction buffer by a validity designator which designates that the presently referenced word is the correct one.

Growing community of inventors

Roseville, MN, United States of America

John T Rusterholz