Intel Corporation

Other

John T Orton

Xia Dai

Gurbir Singh

Cau L Nguyen

Edwin J Pole, Ii

Keng L Wong

Greg F Taylor

Ravi Nagaraj

Raviprakash Nagaraj

John K Chu

Jagir S Multani

Sanjiv K Mittal

Robert Jecmen

George Geannopuolos

A processor has an external pin that can be asserted to lock in new clock ratio information dynamically. A state machine of the processor defines a stop grant state that is utilized to halt the internal clocking signal of the processor. A storage location, such as a register, is utilized to load new clock frequency information into the clock generator circuit of the processor. De-asserting the external pin of the processor causes the processor to resume normal operations, but at the newly set clock frequency.

Apparatus and method for changing processor clock ratio settings

An apparatus for a low skew, low standby power clock network for a synchronous digital system. The power clock network comprises a reference network, maintaining a reference clock signal, and four clock spines, each with its own respective clock signal. To reduce clock skew within the power clock network (i.e., to keep the clock signals of the clock spines synchronous with the reference clock signal), the present invention employs the use of active and passive delay elements to compensate for such skew. A phase relation extraction logic compares the phase of the clock signals from each respective clock spine to the reference clock signal of the reference network. If it is determined that the clock signals of the spines lag the reference clock signal, the phase relation extraction logic will use an active control driver to &ldquo;speed-up&rdquo; the clock signals of the clock spines. And, if the clock signals of the clock spines lead the reference clock signal, the phase relation extraction logic will use capacitive loadings to &ldquo;slow down&rdquo; such clock signals. Advantageously, the likelihood of the microprocessor achieving its maximum operating potential is greatly enhanced by the synchronization of such signals.

Method and apparatus for a low skew, low standby power clock network

A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.

Changing clock frequency

An apparatus for adjusting phase relation of a plurality of clock signals in a processor. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates a first output based on a phase relation between those clock signals. A controller then adjusts the delay of the clock signals based on the first output of the phase detection circuit and a bit of a delay shift register to synchronize the clock signals within a predefined range. The controller generates a second output if the phase relation between the plurality of clock signals has changed before the adjusting of the delay of the clock signals has occurred. A noise band circuit is configured to receive the second output of the controller and adjust the predefined range in response to the receiving of the second output.

Adaptive filtering scheme for sampling phase relations of clock networks

A planarization process for a double metal very large scale integration (VLSI) technology is disclosed. To compensate for an irregular surface topology encountered in a dielectric medium between the two metals, a CVD dielectric layer and a glass layer are first deposited above the first metal. Then an etch-back process is used to uniformly etch back the CVD dielectric and the glass layers at the same rate, leaving a planarized surface for subsequent deposition of a second dielectric layer and a second metal layer.

Surface planarization method for VLSI technology

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Los Altos, CA, United States of America

John T Orton