Micron Technology Incorporated

Ovonyx Memory Technology, LLC

Round Rock Research, LLC

Other

Micro Technology, Inc.

John T Moore

Terry L Gilton

Kristy A Campbell

Scott Jeffrey DeBoer

Joseph F Brooks

Mark Fischer

Ronald Allen Weimer

Kevin L Beaman

Guy T Blalock

Gurtej S Sandhu

Fernando N Gonzalez

J Brett Rolfson

Neal R Rueger

Don Carl Powell

Jiutao Li

Jeff A Mckee

David L Chapek

Randhir P S Thakur

R Jacob Baker

Ardavan Niroomand

Annette L Martin

Ron Weimer

Glen Earl Hush

Mark Alan Helm

Allen McTeer

Brenda D Kraus

Jun Liu

Randhir P Thakur

Li Li

Rita J Klein

Kei-Yu Ko

Scott J Deboer

Steve W Bowes

Karen T Signorini

Patricia C Elkins

Jake Baker

Terry L Giltom

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Semiconductor memory device structure

A semiconductor memory device and front-end method of fabricating nickel plated caps over bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. In some examples, the method and device include one or more conductive and insulating layers formed over a substrate, and a plurality of memory cells over the conductive and insulating layers.

A memory device structure includes circuitry formed over a substrate and at least one insulating portion formed over said circuitry, each of which includes a plurality of openings. The memory device also includes a plurality of electrical connections formed in respective openings of the plurality of openings of the at least one insulating portion, at least one bond pad formed within at least one of the at least one insulating portion, and a cap formed over the at least one bond pad.

Memory device structure

Method of forming a memory device

The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GeSecomposition.

Silver-selenide/chalcogenide glass stack for resistance variable memory and manufacturing method thereof

A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

Use of dilute steam ambient for improvement of flash devices

The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to one embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between two glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GeSecomposition. According to another embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between chalcogenide glass layers and further having a silver layer above at least one of said chalcogenide glass layers and a conductive adhesion layer above said silver layer. According to the another embodiment of the invention, a resistance variable memory element is provided having a first chalcogenide glass layer, a silver layer over said chalcogenide glass layer, a second chalcogenide glass layer over said silver layer, a second silver layer over said second chalcogenide glass layer, and a conductive adhesion layer over said a second silver layer.

Layered resistance variable memory device and method of fabrication

Silver-selenide/chalcogenide glass stack for resistance variable memory

The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400&#xb0; C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.

Method of forming a nitrogen-enriched region within silicon-oxide-containing masses

Method of forming a bond pad

The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 &#x212b; above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.

Method of forming a structure over a semiconductor substrate

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Boise, ID, United States of America

John T Moore