Micron Technology Incorporated

Other

Round Rock Research, LLC

John Stuart Mullin, Sr

Brent Keeth

Layne G Bunker

Bohr-Winn Shih

Ronald L Taylor

Larry Duane Kinsman

Frank F Ross

Raymond J Beffa

Brian L Johnson

Scott J Demer

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

256 Meg dynamic random access memory

An initial condition (IC) behavior module is described for use in a hardware definition language simulation system which operates in two phases. In the first phase, the IC module sets an initial logic condition onto a user-selected node which is to be monitored. The IC module will release the initial condition and then test the node value to determine if the simulation system is able to resolve the node. Alternatively, the IC module may release the node if a user-defined IC time period passes. In the second phase, the IC module monitors the node and reports an error message if the simulated node value becomes unacceptable.

Simulated circuit node initializing and monitoring

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. In certain of the gap cells, multiplexors are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data writes muxes for providing data to the array I/O blocks. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

256 meg dynamic random access memory having a programmable multiplexor

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

A method and system for producing property forms for use in creating design schematics for an integrated circuit using computer-aided design apparatus wherein property forms are produced using a unique sophisticated cell library. The library includes a parameter database that includes base level component description format parameters which provide all of the information that is needed for creating the parameter labels, prompts, data boxes, selectors, etc. for property forms for each logic gate defined in a cell library and for a plurality of operating modes. This allows a single cell library to be used in the creation of a design schematic while permitting parameters of all logic gate instances to be specified at any one of three different design levels or modes, including a mode in which only the drive strength of n-channel type devices is specified, a mode in which the drive strengths of N and P type devices are specified, and a mode in which all of the parameters of all devices are specified. The information displayed on the property form can be customized by the user by entering customizing values for one or more of the base level parameters.

Growing community of inventors

Boise, ID, United States of America

John Stuart Mullin, Sr