Arm Limited

John Stuart Kelly

Peter Guy Middleton

Michael Thomas Kilpatrick

Mark Allen Silla

A cache memory 18 is formed of a content addressable memory 20 and a cache RAM 22. The content addressable memory 20 is divided into two or more sections by an AND gate array 28 that serves to selectively either block or unblock the bit lines 26 that supply an input data word to the bit storage and comparison cells 34 of the content addressable memory 20. The generation of match signals for each section is also selectively blocked by preventing the match signal discharge to ground. The match signals from a blocked section are not passed to the RAM 22. The AND gate array 28 and match signal disable may be controlled by the least significant bit of the input data word, higher order bits of the input data word or may be controlled by a bit selected by program control from among the bits of the input data word. When a portion of the bit lines 26 are blocked by the AND gate array 28, then the capacitance of the bit lines 26 that need to be driven is reduced and the number of match lines discharged is halved thereby reducing power consumption.

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Saffron Walden, United Kingdom

John Stuart Kelly