International Business Machines Corporation

Dell Products Inc.

John Steven Dodson

Ravi Kumar Arimilli

Jerry Don Lewis

Guy L Guthrie

James Stephen Fields, Jr

Derek E Williams

Leo James Clark

Lakshminarayana Baba Arimilli

Eric Eugene Retter

William John Starke

Jody B Joyner

Jeffrey A Stuecheli

Kenneth Lee Wright

Stephen J Powell

Benjiman L Goodman

Brad William Michael

Patrick James Meaney

Glenn David Gilda

Gary A Van Huben

Warren Edward Maule

John Michael Kaiser

Timothy Michael Skergan

Karthick Rajamani

Marc Avery Gollub

Irving G Baysah

Lakshminarayanan Baba Arimilli

Sanjeev Ghai

Vesselina K Papazova

Scot H Rider

Mark Andrew Brittain

Malcolm Scott Allen-Ware

Gregory Scott Still

Todd Jon Rosedahl

Balaram Sinharoy

Luis Alfonso Lastras-Montano

Bulent Abali

Hillery C Hunter

Robert Alan Cargnoni

Miles Robert Dooley

Moinuddin K Qureshi

Lawrence D Curley

Steven J Hnatko

James Charles Gregerson

Didier R Louis

Gary Alan Morrison

Kevin Charles Gower

Michael Stephen Floyd

Frank David Ferraiolo

Ashish Jagmohan

Michele M Franceschini

Adam J McPadden

Srinivasan Ramani

Jordan Ross Keuseman

Steven Powell

Mark R Hodges

Vance Edward Corn

Scott Alan Lenharth

Benjamin Lee Goodman

Lilith Hale

A memory controller comprises a system bus interface that connects the MC to a system processor, a system memory interface that connects the MC to a system memory, a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE), read buffer logic, dynamic controls that are used by the read buffer logic, and an MC processor comprising at least one extended prefetch machine (EPM), each corresponding to one of the at least EPRBEs, where the MC processor is configured to allocate and deallocate EPRBEs and RBEs according to an allocation method using the dynamic controls.

Dynamically allocating memory controller resources for extended prefetching

Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.

Tracking address ranges for computer memory errors

Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.

Performing error correction in computer memory

A data processing system includes a plurality of processing units and a system memory coupled to a memory controller. The system memory includes a persistent memory device and a non-persistent cache interposed between the memory controller and the persistent memory device. The memory controller receives a flush request of a particular processing unit among the plurality of processing units, the flush request specifying a target address. The memory controller, responsive to the flush request, ensures flushing of a target cache line of data identified by target address from the non-persistent cache into the persistent memory device.

Data flush of a persistent memory cache or buffer

A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Scalable data collection for system management

Managing entries in a mark table of computer memory errors including identifying at least two mark table entries as candidates for merger, wherein each mark table entry indicates an error at a location in a computer memory; and merging the identified mark table entries into a single mark table entry, including removing one of the identified mark table entries from the mark table.

Managing entries in a mark table of computer memory errors

Confirming memory marks indicating an error in computer memory including detecting, by memory logic responsive to a memory read operation, an error in at a memory location; marking, by the memory logic in an entry in a hardware mark table, the memory location as containing the error, the entry including one or more parameters for correcting the error; and retrying, by the memory logic, the memory read operation, including: responsive to again detecting the error in the memory location, determining whether the error is correctable at the memory location using the parameters included in the entry; and if the error is correctable at the memory location using the one or more parameters included in the entry, confirming the error in the entry of the hardware mark table.

Confirming memory marks indicating an error in computer memory

A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Dynamically adjusting read data return sizes based on interconnect bus utilization

A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)-way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.

Probabilistic associative cache

A memory system comprises memory devices coupled to a memory controller via a memory interface bus, the memory controller for receiving one or more memory requests via an interconnect. The memory controller tracks utilization of the memory interface bus for reads from the memory devices for a selection of the one or more memory requests during a time window. The memory controller, responsive to detecting utilization of the memory interface bus for reads during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of data to be accessed from the memory devices by at least one read operation, the reduced data size selected from among at least two read data size options for the at least one read operation of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Dynamically adjusting read data return sizes based on memory interface bus utilization

Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

Memory queue handling techniques for reducing impact of high-latency memory operations

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Pflugerville, TX, United States of America

John Steven Dodson