Agilent Technologies, Inc.

Other

Hewlett-packard Company

John Stephen Walther

Robert Campbell Aitken

Jeff Rearick

Fidel Muradali

Lee O Fleming

Stuart L Whannel

Haluk Konuk

Garrett O'Brien

Ismed D S Hartanto

Ismed D S Hartano

A system and method are disclosed for editing netlists described in a hardware description language (HDL). In one embodiment, a netlist is provided and a changes module is provided. The changes module contains a set of changes associated with the netlist. A tool, such as a netlist compiler, then edits the netlist using the changes described in the changes module. The changes module may be used on subsequent, or different, versions of the netlist where the netlist element changed by the changes module are the same. In this manner, repeated manual editing of a netlist, may be significantly reduced.

Batch editor for netlists described in a hardware description language

The present disclosure describes a technique for debugging an integrated circuit having a parallel scan-chain architecture. Blocking circuits are introduced at the inputs and/or outputs of scan-chain branches. The blocking circuits allow the inputs to and/or the outputs from the scan-chain branches to be selectively blocked. This allows individual scan-chain branches to be isolated and debugged.

Technique for debugging an integrated circuit having a parallel scan-chain architecture

Simultaneously increasing the effective frequency of scanning operations and increasing memory capacity can be achieved by multiplexing multiple state data into each tester memory location. A system includes a source for providing scan-in sequences of state data as input stimuli into a device under test (DUT) and expected scan-out sequences of state data. A vector processor receives the scan-in sequences and expected scan-out sequences and enables multiplexed state data exchanges in which the multiple multiplexed state data vectors are manipulated at the tester cycle rate, while the DUT manipulates the bits at its faster device cycle rate. For a multiplexing factor of m, the device cycle rate may be m times the tester cycle rate. The selection of the multiplexing factor is based upon the storage capacity of individual tester memory locations and upon enabling the effective vector exchange rate to be m times the tester cycle rate.

Scan multiplexing for increasing the effective scan data exchange rate

An integrated circuit is provided with Fully Automated Scan Testing (FAST)-lite flip-flop. The integrated circuit has data, scan in, master-hold, clock, scan-into-master, and master to-scan-out inputs. A first transistor circuit is connected to the data, master-hold, and clock inputs and has a first transistor circuit output. A second transistor circuit is connected to the can in and scan-into-master inputs and has a second transistor circuit output. A first flip-flop is connected to the first transistor circuit and second transistor circuit outputs and has a first flip-flop output. A third transistor circuit is connected to the second transistor circuit output and the master-to-scan-out input and has a third transistor circuit output. A second flip-flop latch is connected to the third transistor circuit output has a second flip-flop output. The FAST-lite flip-flop uses the normal functionality of the first flip-flop and second flip-flop to operate either in a normal mode or a test mode for scan testing. The FAST-lite flip-flop is so designated because it uses one less flip-flop than the prior art FAST flip-flop.

Integrated circuit with scan flip-flop

This invention improves and simplifies prior art systems for automatic test generation methodologies. In this invention, combinational logic is used to prevent opposing tristate bus drivers from simultaneously providing a logic signal on a common bus during testing of an integrated circuit. The combinational logic also ensures that at most one tristate buffer is enabled at all times during testing to ensure the common bus is at either a full logical 1, logical 0, or non-driven state. By preventing opposing drive signals being applied to the common bus and thus ensuring the bus is at a full logical 1 or logical 0 state when driven, automatic test generation programs can accurately generate test vectors for the integrated circuit.

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Sunnyvale, CA, United States of America

John Stephen Walther