Nvidia Corporation

Microsoft Technology Licensing, LLC

Silicon Graphics, Incorporated

Other

Graphics Properties Holdings, Inc.

Nvida Corporation

Graphic Properties Holdings, Inc.

John Stephen Montrym

John Erik Lindholm

Steven E Molnar

Douglas A Voorhies

James M Van Dyke

Simon S Moy

David B Kirk

Kevin Dawallu

Matthew Nicholas Papakipos

David Brian Glasco

Paolo Enrique Sabella

Nicholas J Foskett

Mingjian Yang

Henry Packard Moreton

Sean Jeffrey Treichler

John M Danskin

Robert A Drebin

Lingfeng Yuan

Jerome Francis Duluk, Jr

Emmett Michael Kilgariff

Franklin C Crow

Christopher D S Donham

Mark S Peercy

Christopher J Migdal

David L Dignam

John Milligan Airey

Richard A Silkebakken

Michael B Nagy

Walter E Donovan

Shane J Keil

Mark Stefan Grossman

Michael B Diamond

Mark J French

Gregory M Eitzmann

Fred Gruner

Edward C Chen

Brett Coon

John H Edmondson

Bengt-Olaf Schneider

Mark M Leather

Gary M Tarolli

Anthony Michael Tamasi

Craig Michael Wittenbrink

Robert C Keller

Philip Payman Shirvani

Richard Gavin Bramley

Danny Loh

Danny D Loh

Chi-Shung Wang

Charles Chew-Yuen Young

Franck Diard

Ziyad Sami Hakura

Jonah Matthew Alben

Brian K Langendorf

Eric Brian Lum

Brad W Simeral

Patrick Rene Marchand

Stephen Donald Lew

Cass Watson Everitt

Nirmal Raj Saxena

Abraham Benjamin De Waal

Michael C Shebanow

Philippe Lacroute

Alexander Lev Minkin

Michael Timothy Jones

David Kirk McAllister

Rui Bastos

Eric T Anderson

Barry A Wagner

Harold Robert Feldman Zatz

Vimal S Parikh

Andrew J Tao

Michael Brian Cox

Daniel P Wilde

Justin S Legakis

Jen-Hsun Huang

Brian D Hutsell

Walter Robert Steiner

Christopher Thomas Cheng

James L Foran

Ian M Williams

James E Margeson, Iii

Yan Yan Tang

Justin Cobb

Matthew J Craighead

Gregory C Buchner

Scott R Whitman

Jeffrey J Irwin

Bruce Cory

Dale Ah Tye

Blanton Scott Kephart

Stefan Scotzniovsky

Sean J Treicher

Nathaniel C Voorhies

An autonomous driving system could create or exacerbate a hazardous driving situation due to incorrect machine learning, algorithm design, sensor limitations, environmental conditions or other factors. This technology presents solutions that use machine learning to detect when the autonomous driving system is in this state e.g., erratic or reckless driving and other behavior, in order to take remedial action to prevent a hazard such as a collision.

Detection of hazardous driving using machine learning

A method, computer readable medium, and system are disclosed for error coping. The method includes the steps of receiving, by a processing unit, a set of program instructions including a first program instruction that is responsive to error detection, detecting an error in a value of a first operand of the first program instruction, and determining that error coping execution is selectively enabled for the first instruction. The value for the first operand is replaced with a substitute value and the first program instruction is executed by the processing unit.

Error mitigation for resilient algorithms

A technique for multiresolution consistent rasterization in which a setup unit calculates universal edge equations for a universal resolution. A rasterizer evaluates coverage data for two different resolutions based on the edge equations. The rasterizer evaluates coverage data for different effective pixel sizes&#x2014;a large pixel size and a small pixel size. Optionally, the rasterizer may determine a first set of coverage data by performing conservative rasterization to determine coverage data for large pixels. Optionally, the rasterizer may then determine a second set of coverage data by performing standard rasterization for small pixels. Optionally, for the second set of coverage data, the rasterizer may evaluate only the small pixels that are within large pixels in the first set of coverage data that evaluate as covered.

Multiresolution consistent rasterization

One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.

Error detection and correction for external DRAM

In a raster stage of a graphics pipeline, a method for rasterizing non-rectangular tile groups. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level by generating a non-rectangular footprint comprising a set of pixels related to the graphics primitive. The graphics primitive is then rasterized at a second level by accessing the set of pixels and determining covered pixels out of the set of pixels. The raster stage subsequently outputs the covered pixels for rendering operations in a subsequent stage of the graphics processor.

Method for rasterizing non-rectangular tile groups in a raster stage of a graphics pipeline

A system and method for tracking and reporting texture map levels of detail that are computed during graphics processing allows for efficient management of texture map storage. Minimum and/or maximum pre-clamped texture map levels of detail values are tracked by a graphics processor and an array stored in memory is updated to report the minimum and/or maximum values for use by an application program. The minimum and/or maximum values may be used to determine the active set of texture map levels of detail that is loaded into graphics memory.

Determining a working set of texture maps

The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors, including if the die has a defective component. An indication of the defective functional component identification is received. A determination is made if the defective functional component is one of a plurality of similar functional components that can provide the same functionality. The other similar components can be examined to determine if they are parallel components to the defective functional component. The defective functional component is disabled if it is one of the plurality of similar functional components and another component can handle the workflow that would otherwise be assigned to the defective component. Workflow is diverted from the disabled component to other similar functional components.

Integrated circuit configuration system and method

The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors. In one embodiment, manufacturing yields, compatibility characteristics, performance requirements, and system health (e.g., the number of components operating properly) are factored into changes to the operational characteristics of functional components. In one exemplary implementation, the changes to operational characteristics of a functional component are coordinated with changes to other functional components. Workflow scheduling and distribution is also adjusted based upon the changes to the operational characteristics of the functional components. For example, a functional component configuration controller changes the operational characteristics settings and provides an indication to a workflow distribution component. The workflow distribution component changes the workflow schedule based upon the operational characteristics settings (e.g., work flow is diverted to or away from functional components).

System and method for configuring semiconductor functional circuits

The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present invention system and method enable integrated circuit chips with defective functional components to be salvaged. Defective functional components in the die are disabled in a manner that maintains the basic functionality of the chip. A chip is tested and a functional component configuration process is performed on the chip based upon results of the testing. If an indication of a defective functional component is received, the functional component is disabled. Workflow is diverted from disabled functional components to enabled functional components.

System and method for increasing die yield

The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional component reconfiguration request process is engaged in wherein a system requests a reconfiguration code from a remote centralized resource. A reconfiguration code production process is executed in which a request for a reconfiguration code and a permission indicator are received, validity of permission indicator is analyzed, and a reconfiguration code is provided if the permission indicator is valid. A die functional component configuration process is performed on the die when an appropriate reconfiguration code is received by the die. The functional component configuration process includes directing alteration of a functional component configuration. Workflow is diverted from disabled functional components to enabled functional components.

System and method for remotely configuring semiconductor functional circuits

A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.

Parallel array architecture for a graphics processor

A memory cell reconfiguration process is performed in accordance with the operational characteristic settings determined based upon the results of analysis and/or testing of memory cell operations. The memory circuit can include a plurality of memory cells and memory cell configuration controller. The memory cells store information associated with a variety of operations. The memory cell configuration controller coordinates selective enablement and disablement of each of the plurality of memory cells, which can be done on a subset or group basis (e.g., enables and/or disables memory cells on a word length or row by row basis). The address mapping can be adjusted so that the memory space appears continuous to external components. The memory cell configuration controller can also forward configuration information to upstream and/or downstream components that can adjust operations to compensate for the memory cell configuration (e.g., to prevent overflow).

Functional component compensation reconfiguration system and method

A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for coordinating context memory storage block binds and independently controlling access to the context memory without interference from other engine activities. In one exemplary implementation the context information is included in a block and the memory management unit binds the block to instance memory. The instance memory can be protected memory. The instance memory can also support multiple channels associated with the plurality of engines. In one exemplary implementation, the instance memory includes a pointer to a page table. The instance memory can also include context save and restore data and each one of the plurality of engines initiates a unique block bind by indicating an association between their engine ID and a given block of instance memory.

Memory access management block bind system and method

A memory access technique that provides for overriding a translation lookaside buffer and page table data structure, in accordance with one embodiment of the present invention, includes selectively translating a virtual address directly to a physical address utilizing an adjustment in a context specifier, or translating the virtual address to the physical address utilizing a translation lookaside buffer or page table data structure.

Memory access techniques providing for override of a page table

A method and system are disclosed for antialiased rendering a plurality of pixels in a computer system. The method and system comprise providing a fixed storage area and providing a plurality of sequential format levels for the plurality of pixels within the fixed storage area. The plurality of format levels represent pixels with varying degrees of complexity in subpixel geometry visible within the pixel. A system and method in accordance with the present invention provides at least the following format levels: one-fragment format, used when one surface fully covers a pixel; two-fragment format, used when two surfaces together cover a pixel; and multisample format, used when three or more surfaces cover a pixel. The method and system further comprise storing the plurality of pixels at a lowest appropriate format level within the fixed storage area, so that a minimum amount of data is transferred to and from the fixed storage area. The method and system further comprise procedures for converting pixels from one format level to take into account newly rendered pixel fragments. All formats represent depth values in a consistent manner so that fragments rendered during later rendering passes match depth values resulting from rendering the same primitive in earlier passes. Thus, the invention enables high-quality antialiasing with minimal data transferred to and from the fixed storage area, while supporting multi-pass rendering.

Method and system for efficient antialiased rendering

Growing community of inventors

Los Altos, CA, United States of America

John Stephen Montrym