Intel Corporation

John Stephen Guzek

Robert L Sankman

Deepak Kulkarni

Robert Starkston

Debendra Mallik

Chia-Pin Chiu

Weng Hong Teh

Johanna M Swan

Ravindranath Vithal Mahajan

Ravi V Mahajan

Javier Soto Gonzalez

Nitin A Deshpande

Ravi Kiran Nalla

Hamid Azimi

Adel A Elsherbini

Sasha N Oster

Drew W Delaney

Victor Prokofiev

Aleksandar Aleksov

Cengiz Ahmet Palanduz

Nicholas Randolph Watts

Feras Eid

Qing Ma

Kemal Aygun

Omkar G Karhade

Sairam Agraharam

Charles A Gealer

Shan Zhong

Tannaz Harirchian

Timothy E McIntosh

Ravi Pillarisetty

Christopher J Jezewski

Islam A Salama

William J Lambert

Sanka Ganesan

Rajasekaran Swaminathan

Robert M Nickerson

Pramod Malatkar

Sriram Srinivasan

Sriram Muthukumar

Mohit Mamodia

Christopher J Nelson

Edward A Zarbock

Mengzhi Pang

Russell K Mortensen

Tyler N Osborn

Joel A Auernheimer

Suresh V Pothukuchi

Ian A Young

Thorsten Meyer

Shawna M Liff

Telesphor Kamgaing

Rahul N Manepalli

Saikumar Jayaraman

Vijay K Nair

Mihir K Roy

James Chris Matayabas, Jr

Ram S Viswanath

Yonggang Li

Yoshihiro Tomita

Leonel R Arana

John C Johnson

Charan K Gurumurthy

Klaus Reingruber

Dustin P Wood

Yongki Min

Yidnekachew S Mekonnen

Michael Walk

Yosuke Kanaoka

Oswald L Skeete

Eric C Palmer

Patrick Nardi

Brent M Roberts

Nitesh Nimkar

Keith D Jones

Mahadevan Survakumar

Min Tao

Javier Solo Gonzalez

Ravi K Nailla

Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.

Embedded die on interposer packages

Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Localized high density substrate routing

A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Embedded semiconductive chips in reconstituted wafers, and systems containing same

A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

Semiconductor package having spacer layer

Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.

Electro-magnetic interference (EMI) shielding techniques and configurations

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

Recessed and embedded die coreless package

Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.

Logic die and other components embedded in build-up layers

Growing community of inventors

Chandler, AZ, United States of America

John Stephen Guzek