General Electric Company

Efficient Power Conversion Corporation

Lockheed Martin Corporation

General Electric Corporation Gmbh

Other

Haier US Appliance Solutions, Inc.

John Stanley Glaser

Michael Andrew De Rooij

Ramanujam Ramabhadran

Harry Kirk Mathews, Jr

Eladio Clemente Delgado

Joseph Lucian Smolenski

Austars Raymond Schnore, Jr

Brian Lynn Rowden

Jeffrey Joseph Nasadoski

Stephen L Colino

Robert Louis Steigerwald

Canan Uslu Hardwicke

Regan Andrew Zane

Ljubisa Dragoljub Stevanovic

Michael Joseph Schutten

Richard Alfred Beaupre

Judson Sloan Marte

Fengfeng Tao

David C Reusch

Joseph Taher Mossoba

Juan Manuel Rivas Davila

Gerald Burt Kliman

William James Premerlani

Timothy Scott Shaffer

Stanton Earl Weaver, Jr

Charles Erklin Seeley

Antonio Caiafa

Peter Almern Losee

Walter Whipple

Juan Antonio Sabate

Seyed Gholamali Saddoughi

Kyle Erik Litz

John Raymond Krahn

Satish Prabhakaran

Yehuda Daniel Levy

Said Farouk Said El-Barbari

Ravi Ananth

Robert Carl Murray

Ahmet Gun Erlat

Abdelkrim Younsi

Edward Lee

Robert James Thomas

Michael Chapman

Xiaochun Shen

Adam Gregory Pautsch

George Charles Goodman

Aharon Yakimov

Oliver Gerhard Mayer

Maja Harfman-Todorovic

Yuanzhe Zhang

Han Peng

Howard Leroy Lester

Said Farouk El-Barbari

Frank Jakob John Mueller

Timothy Joseph Kottak

Christian Marie Anton Heller

A physical arrangement of at least two power switches and at least one capacitor in a power loop. At least one of the switches is formed of at least two parallel electronic devices, such as transistors. The arrangement minimizes total power loop impedance and results in approximately equal impedance in each parallel branch of the switch formed of two parallel devices, thereby resulting in approximately equal currents in the switches.

Half-bridge circuits with symmetrical layout of parallel transistors and capacitors

A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously.

Multi-channel pulse current generator with charging

A highly efficient, multi-layered, single component sided circuit board layout design providing reduced parasitic inductance for power switched circuits. Mounted on the top board are one or more transistor switches, one or more loads, and one or more capacitors. The switches and capacitors form a loop with very low parasitic inductance. The loads may be a part of the loop, i.e. in series with the switches and capacitors, or may be connected to two or more nodes of the loop to form additional loops with common vertices. Parallel wide conductors carry the switch load current resulting in a low inductance path for the power loop. The power loop and gate loop current travel in opposite directions and are well separated, minimizing common source inductance (CSI) and maximizing switching speed.

Low parasitic inductance structure for power switched circuits

A common gate amplifier circuit configured to provide decreased voltage transients in the input voltage due to reverse gain. A second FET transistor is connected in series with a first FET of the common gate amplifier to function as an additional capacitive voltage divider between the amplifier output and the amplifier input without influencing the input or output currents. The first FET transistor, coupled to the amplifier input, may be a low voltage FET and smaller than the second FET transistor, which is coupled to the amplifier output. Both FET transistors are preferably enhancement mode GaN FET transistors and may be integrated into a single semiconductor chip with a single internal bias voltage divider.

Common gate amplifier with high isolation from output to input

A current measurement circuit for determining a start time t, an end time t, and/or a peak time tfor a current pulse passing through a current conductor. The current measurement circuit includes a pickup coil and a threshold crossing detector. The pickup coil generates a voltage V' proportional to a magnetic field around the conductor, which is proportional to a change in current over time. The threshold crossing detector compares V&#x2032; and a threshold voltage and generates an output signal indicative of a transition time and whether a slope of V&#x2032; is positive or negative. The current measurement circuit can also include an integrator and a sample and hold circuit. The integrator integrates V&#x2032; over time and generates an integrated signal V. The sample and hold circuit compares Vto tand generates a second output signal which can be used to measure the pulse current.

Magnetic field pulse current sensing for timing-sensitive circuits

A current pulse generator circuit configured to be monolithically integrated into a single semiconductor die and provide high pulsing frequencies. A first GaN FET transistor controls the charging of a capacitor in a boost converter. A second GaN FET transistor controls the discharging of the capacitor through a load, such as a laser diode, connected to the boost converter. Both GaN FET transistors are preferably enhancement mode GaN FETs and may be integrated into the single semiconductor die, together with gate drivers. The diode in a conventional boost converter circuit can also be implemented in the present invention as a GaN FET transistor, and also integrated into the single semiconductor die.

Current pulse generator with integrated bus boost circuit

A circuit for providing an adjustable output driver current for use in LiDAR or other similar GaN driver applications. The circuit creates an appropriate gate-to-source voltage, V, for a high-current GaN driver FET to obtain a desired, high slew-rate driver current, I. An externally provided reference current is used to create the required Vfor the driver FET, which is stored on an external capacitor. The value of the capacitor far exceeds the relatively low input-capacitance of the GaN driver FET. When a pulse Iof desired value is needed, the voltage on the capacitor is impinged upon the gate of the driver FET, thereby creating the desired I. The reference charging circuit replenishes any charge lost on the capacitor, so that the same desired Ican be obtained on the next command pulse.

GaN based adjustable driver current circuit

A drive circuit for a half bridge transistor circuit formed of enhancement mode GaN transistors. A shunt diode is connected to the bootstrap capacitor at a node between the bootstrap capacitor and ground, the shunt diode being decoupled from the midpoint node of the half bridge by a shunt resistor. The shunt diode advantageously provides a low voltage drop path to charge the bootstrap capacitor during the dead-time charging period when both the high side and low side transistors of the half bridge are off.

Bootstrap capacitor over-voltage management circuit for GaN transistor based power converters

A circuit for an RF switch using FET transistors that largely cancels the non-linearity of the Cof the FETs over a majority of the signal range, and reduces distortion. The RF switch includes two substantially identical FETs. The source of one FET is connected to the drain of the other FET and the node formed comprises one terminal of the switch. Two substantially identical capacitors are connected in series with each other and in parallel with the FETs, and the node thus formed comprises the second terminal of the switch. The capacitors are selected such that they have negligible impedance at AC frequencies for which the switch is expected be used, and in particular a much lower impedance than Cof each FET. A voltage source with a series impedance is also connected in parallel with the capacitors and the two FETs.

Low distortion RF switch

A universal power adapter includes a power converter configured to generate an output power based on a switching frequency of the power converter. The universal power adapter also includes a frequency controller operatively coupled to the power converter and configured to control the switching frequency of the power converter. The universal power adapter further includes a switch capacitor circuit having a plurality of capacitive elements, operatively coupled to the power converter. The switch capacitor circuit is configured to switch between the plurality of capacitive elements. The universal power adapter also includes a capacitance controller operatively coupled to the switch capacitor circuit and configured to control the switch capacitor circuit to control switching between the plurality of capacitive elements to maintain a control parameter within a threshold range of.

Universal power adapter and an associated method thereof

A system includes a SiC semiconductor power device; a power supply board that is configured to provide power to a first gate driver board via a connector; the first gate driver board that is coupled and configured to provide current to the SiC semiconductor power device, wherein the first gate driver board is coupled to the power supply board via the connector, and wherein the first gate driver board is separated from the power supply board; and an interconnect board that is coupled to the first gate driver board, wherein the interconnect board is configured to couple the first gate driver board a second gate driver board.

Ultra high performance silicon carbide gate drivers

Systems and methods are disclosed for reducing an interwinding capacitance current in a transformer. In certain embodiments, the transformer includes a coupling winding and a primary winding that encircles a portion of the coupling winding. Additionally, the transformer includes a secondary winding that encircles a portion of the coupling winding. The transformer includes a shield terminal which is electrically coupled to the coupling winding. The shield terminal directs currents, such as interwinding capacitance currents, in the coupling winding to ground.

Method for reducing interwinding capacitance current in an isolation transformer

A system for driving a piezoelectric load includes a direct current (DC) voltage source and a bi-directional DC-to-DC converter having a primary side coupled to the DC voltage source and a secondary side and comprising a control input configured to receive a first control signal configured to control conversion of a first voltage on the primary side of the bi-directional DC-to-DC converter to a second voltage on the secondary side of the bi-directional DC-to-DC converter. The driver system also includes a capacitor coupled to the secondary side of the bi-directional DC-to-DC converter and configured to remove a DC offset of the second voltage and includes a reactive load having a first terminal coupled to the capacitor and a second terminal coupled to the secondary side of the bi-directional DC-to-DC converter.

System for driving a piezoelectric load and method of making same

A driver system comprises a direct current (DC) voltage source and a first bi-directional DC-to-DC converter having a primary side coupled to the DC voltage source and a secondary side and configured to convert a first voltage on the primary side to a second voltage on the secondary. The driver system also comprises a second bi-directional DC-to-DC converter having a primary side coupled to the DC voltage source and a secondary side coupled to the secondary side of the first bi-directional DC-to-DC converter and configured to convert the first voltage on the primary side to a third voltage on the secondary. The first and second bi-directional DC-to-DC converters are capable of boosting the first voltage, and the second control signal is a complement of the first control signal. A voltage difference between the second and third voltages comprises an output voltage that comprises an amplification of the first control signal.

An induction cooktop appliance is provided. The induction cooktop appliance includes an induction heating element and a metal top panel positioned above the induction heating element for supporting cooking utensils thereon. The metal top panel defines an opening above the induction heating element. The opening can limit or regulate eddy currents within the metal top panel.

Induction cooktop appliance

Growing community of inventors

Niskayuna, NY, United States of America

John Stanley Glaser