Advanced Micro Devices Corporation

Unity Semiconductor Corporation

Hefei Reliance Memory Limited

Adesto Technologies Corporation

Advance Micro Devices, Inc.

John Sanchez

Christophe J Chevallier

Wayne I Kinney

Darrell Rinerson

Steven W Longcor

Edmond R Ward

Steve Kuo-Ren Hsia

Philip F S Swab

Christy Mei-Chu Woo

Amit P Marathe

Darrell M Erb

Wei Ti Lee

Foroozan Sarah Koushan

John Ross Jameson, Iii

Minh Van Ngo

Steven C Avanzino

Suzette Keefe Pangrle

Yi Ma

Venkatesh P Gopinath

Ercan Adem

Christine Hau-Riege

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

Memory element with a reactive metal layer

In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof

A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO-LSCoO or LaNiO-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

The reliability and performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate, are enhanced by a method for reliably depositing a barrier layer selective to the metallization patterns. The method comprises forming a sacrificial dielectric layer above a substrate. Metallization patterns are formed in the sacrificial dielectric layer. The barrier layer is selectively deposited on the metallization patterns. Portions of the barrier material undesirably deposited on the sacrificial dielectric layer are removed by removing the sacrificial dielectric layer, thus preventing bridging of adjacent metallization features by the barrier layer portions. An interlevel dielectric layer is then formed in place of the sacrificial dielectric layer. The selectively deposited barrier layer advantageously reduces parasitic capacitance between metallization features in comparison to a conventional blanket-deposited silicon nitride barrier layer.

Method of forming a selective barrier layer using a sacrificial layer

An interconnect test structure for characterizing electromigration includes a test line and a feeder coupled to the test line by a via structure. A width of the feeder line is greater than a width of the test line. Slots are formed in the feeder line for preventing formation of a stress-induced void at an interface between the feeder line and the via structure. Thus, an increase in resistance of the test structure is attributable to electromigration failure of the test line.

Interconnect test structure with slotted feeder lines to prevent stress-induced voids

A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 &angst;, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 &angst;, and/or as discontinuous regions of clusters of atoms on sides of the opening.

Copper interconnect with improved barrier layer

Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first silicon carbide, and a second silicon carbide layer on the silicon-rich layer. Embodiments include sequentially depositing a porous low-k dielectric layer over a lower capped Cu line, depositing the graded middle-etch stop layer, depositing a porous low-k dielectric layer on the graded middle-etch stop layer, forming a dual damascene opening exposing the silicon-rich surface at the bottom of the trench opening, depositing a seed layer, depositing a barrier middle layer, such as Ta or a Ta/TaN composite, and filling the opening with Cu.

Graded low-k middle-etch stop layer for dual-inlaid patterning

Growing community of inventors

Palo Alto, CA, United States of America

John Sanchez