Vtc Inc.

Other

Intersil Corporation

John S Shier

John D Leighton

Tuan V Ngo

Douglas R Peterson

Matthew F Schmidt

The present invention implements a novel emitter scheme that maximizes the emitter perimeter to emitter area ratio of an integrated circuit transistor, thereby achieving improved low noise characteristics over the prior art. Emitter regions are disposed in the transistor in discrete 'dotted ' segments. The dotted emitter segments may be realized by etching into emitter regions defined by an appropriately formed photoresistive overlay, which can be modified without fabrication process changes. The effect is to reduce the total emitter area by half, while maintaining the total emitter perimeter unchanged. As a result, the noise-capacitance product of the transistor is reduced, improving the overall performance of the transistor.

Method of fabricating a segmented emitter low noise transistor

The present invention implements a novel emitter scheme that maximizes the emitter perimeter to emitter area ratio of an integrated circuit transistor, thereby achieving improved low noise characteristics over the prior art. Emitter regions are disposed in the transistor in discrete 'dotted' segments. The dotted emitter segments may be realized by etching into emitter regions defined by an appropriately formed photoresistive overlay, which can be modified without fabrication process changes. The effect is to reduce the total emitter area by half, while maintaining the total emitter perimeter unchanged. As a result, the noise-capacitance product of the transistor is reduced, improving the overall performance of the transistor.

Segmented emitter low noise transistor

A data storage system for storing and retrieving data signals on magnetic medium includes a magnetic transducer, a controller for issuing instructions, and a pre-amplifier adaptive to data storage parameters. The pre-amplifier includes a read amplifier having an adjustable gain, a write driver having an adjustable current source, and a serial shift register responsive to the instructions to selectively operate the read amplifier and the write driver and to issue control signals to first and second digital-to-analog converters to adjust the gain of the read amplifier and the current source of the write driver. Preferably first and second multiplexers are responsive to the control signals to select one of a plurality of magnetic transducers.

Programmable pre-amplifier using a serial shift register to output a

A write circuit for driving a magnetic head in a magnetic storage system which greatly improves the voltage swing across the magnetic head. The write circuit includes data input for receiving data input signals, a predriver current source, a predriver circuit, and a write driver circuit. The predriver circuit is connected to the data input and has first and second predriver current paths. The predriver current paths are connected to a predriver current source. The predriver circuit directs current from the predriver current source through the first and second predriver current paths as a function of the data input signals. The write driver circuit has first and second write currents paths connected across the magnetic head. The first write current path directs current through the magnetic head in a first direction and the second write current path directs current through the magnetic head in a second direction, opposite to the first direction. The predriver circuit and the write driver circuit are connected together in a current mirror configuration to mirror the predriver current from the first and second predriver currents paths into the first and second write driver currents paths, respectively.

Write circuit having current mirrors between predriver and write driver

A timing synchronizing circuit with a phase locked loop. A multiplexor is employed to cause the phase locked loop to alternate between a self-excited mode for maintaining the frequency of a recovered timing signal and a mode in which state transitions of a baseband data signal are compared with the phase locked loop feedback signal to adjust the frequency of the recovered timing signal.

Timing synchronizing circuit for baseband data signals

A differential charge pump for use in a phase locked loop. The charge pump generates a voltage difference signal proportional to the duration of first and second pulse trains provided by a phase comparator. The charge pump includes a differential amplifier for generating the difference signal, first and second RC filter networks connected between the noninverting and inverting terminals of the differential amplifier and a reference node, respectively. Parallel, all-NPN switching networks apply charging current pulses to the first RC filter network in response to the first pulse train and they apply charging current pulses to the second RC filter network in response to the second pulse train.

Differential charge pump for a phase locked loop

A junction field effect transistor fabricated by a simplified process for incorporation into an integrated circuit including bipolar transistors is disclosed. The JFET comprises an isolated gate region of a first conductivity type with a surface on the integrated circuit and a buried layer beneath the surface to enhance conductivity. A pair of spaced-apart regions of a second conductivity type extend into the gate region form the surface but not into contact with the buried layer. A plurality of ion implanted subsurface channels of the second conductivity type extend between the pair of spaced-apart regions. Between each subsurface channel and the surface is an upper gate region of the first conductivity type, each of which has an enhanced dopant concentration compared with adjacent portions of the gate region. The upper gates are formed through the same mask as the subsurface channels for insuring optimal alignment of the gates with the channels and simplifying fabrication. The resulting JFET also has improved frequency response characteristics.

Short channel junction field effect transistor

A single chip monolithic integrated successive approximation analog-to-digital converter includes a test mode terminal for receiving shift register test mode control signals and successive approximation mode control signals. Digital test data signals are applied to a test data terminal. A trimmable digital-to-analog converter (DAC) is connected to receive digital signals and converts these signals to analog signals of corresponding values. A successive approximation and shift register is coupled to the test mode terminal and the test data terminal. During post-fabrication processing, the successive approximation and shift register operates in a shift register test mode in response to the test mode control signals. Test signals of a known value are serially received and applied in parallel to the DAC. The DAC can then be trimmed to required specifications. The successive approximation and shift register operates in a successive approximation mode in response to successive approximation mode control signals.

Single chip successive approximation analog-to-digital converter with

A resistor network coupling two terminal leads and adapted to be fabricated on an integrated circuit. A plurality of N-sided meshes are each formed by N resistor elements linked at network nodes. Some of the resistor elements can be cut by a laser under computer control to select a desired resistance value of the network.

Mesh network for laser-trimmed integrated circuit resistors

A distributed wye resistor network fabricated on an integrated circuit substrate includes a resistive body coupled between two terminal elements. The resistive body includes a plurality of slots extending therethrough between the terminal elements to form a plurality of discrete resistive links. The resistive body therefore has characteristics of an artificial anisotropically conducting medium. The resistive links have a parabolic length profile. The links can be continuously cut, starting with the shortest link, until parameters of the integrated circuit are brought within desired specifications.

Slotted integrated circuit resistor

A buried load device in an integrated circuit extends between two regions of like conductivity isolated from each other by thick oxide and substrate comprises a channel beneath the oxide and having dimensions defined by a diffused region of opposite conductivity type. The buried channel is formed by impurity migration from an upper epitaxial layer that is oxidized to separate two regions and the connecting channel width is defined by diffused strip regions of opposite conductivity to establish a desired current-voltage relationship thereof.

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Apple Valley, MN, United States of America

John S Shier