International Business Machines Corporation

John S Lechaton

Gurumakonda R Srinivasan

Dominic Joseph Schepis

Harsaran S Bhatia

Shashi D Malaviya

Santosh Prasad Gaur

Janos Havas

Philip M Pitner

Rajiv V Joshi

James Gardner Ryan

Joseph M Mosley

Narasipur G Anantha

Mithkal M Smadi

Joseph S Logan

Jack A Dorler

James L Walsh

Shaw-Ning Mei

Stephen Bruce Brodsky

Bai-Cwo Feng

Thomas A Hansen

George A Kaplita

James A Bondur

Nicholas J Giammarco

Joseph A Bialko

Skinner Logan

A process, compatible with bipolar and CMOS silicon device manufacturing for fabricating complementary buried doped regions in a silicon substrate. An N+ doped region (12) is formed in the silicon substrate by known methods of arsenic doping and drive in. This is followed by depositing a first thin epitaxial silicon cap layer (14), under conditions of minimum N+ autodoping. Part thickness of this first epilayer is converted to oxide (18), and the oxide is patterned to provide apertures in an area where it is desired to form a P+ region. A P source material (20) is deposited and a drive in anneal is used to dope the silicon with P in the areas of the oxide aperture opening. Subsequent to drive in, the dopant source layer and the oxide mask is removed by wet etching. An oxide is regrown on the surface, including the P+ region (22), and subsequently the oxide layer is stripped in dilute hydrofluoric acid. Next a second epitaxial silicon layer (28) is deposited to make up the total epi thickness to a desired value, using process conditions of minimum P doping.

Fabricating planar complementary patterned subcollectors with silicon

A contact is provided in a self-aligned manner to a doped region a semiconductor substrate by first forming a layer of a transition metal-boride compound over a selected region on the substrate. A layer of a transition metal-nitride compound is formed over the layer of transition metal-boride compound, and the structure is heated to drive dopant from the layer of transition metal-boride compound into the substrate. The transition metal-boride/transition metal nitride layers are patterned to leave a contact to the doped region.

Method of making semiconductor device contact including transition

A method for manufacturing a BiCMOS device includes providing a semiconductor substrate including first and second electrically isolated device regions. A layer of insulating material is formed over the first device region, and a layer of conductive material is formed conformally over the device. Portions of the conductive layer are removed to leave a base contact on the surface of the second device region and an insulated gate contact over the surface of the first device region. A FET is formed in the first device region having a channel under the insulated gate. A vertical bipolar transistor is formed in the second device region having a base region contacting the base contact.

BiCMOS process

There is described a process for making a high performance NPN bipolar transistor functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon body wherein the transistor includes an N+ subcollector, an N+ collector reach-through which connects the subcollector to a major surface of the silicon body, a P base region above the subcollector and adjacent to the reach-through region, an N+ emitter region within the base region and extending from the major surface. The base region includes an intrinsic base region located below the emitter region and an extrinsic region located extending from the major surface and adjacent to the emitter region. The extrinsic base preferrably completely surrounds or rings the emitter region. A mask is formed above the major surface and the mask has openings therein only in the areas above major portions of the extrinsic base regions. A P+ type region is formed in the extrinsic base region by ion implanting with a P type dopant to a depth of less than the depth of the N emitter region followed by a short thermal anneal to activate the P dopant. Electrical ohmic contacts are made to the elements of the transistor and the elements are connected in a current switch logic circuit. The use of the high conductivity P+ region in the extrinsic base region closely adjacent to the emitter substantially reduces the extrinsic base resistance. Since the extrinsic base region resistance is reduced, it is possible to reduce the size of the emitter area. Independent doping in the extrinsic base through the mask openings also allows independent control of the intrinsic and extrinsic base resistances. The result of these changes substantially increase the performance of bipolar transistor integrated circuits for current switch logic applications.

High performance integrated circuit having modified extrinsic base

Disclosed is a process for etching semiconductor materials with a high etch rate against an insulator mask using a novel etchant gas mixture. The mixture consists of a chlorocarbon (e.g., CCl.sub.2 F.sub.2, CCl.sub.4 or CCl.sub.3 F), SF.sub.6, O.sub.2 and an inert gas (e.g. He). The preferred gas mixture contains 2/1 ratio of the chlorocarbon to SF6 and the following composition: 1-4% of SF.sub.6, 3-10% of O.sub.2, 74-93% of He and 3-10% of chlorocarbon. The etch rate of silicon (or silicide) against an oxide mask using this etchant gas mixture under normal etching conditions is high, on the order of 30-40. An impressive feature of the process is shape control of trenches by mere manipulation of the RIE system power.

RIE process for etching silicon isolation trenches and polycides with

A fully isolated dielectric structure for isolating regions of monocrystalline silicon from one another and method for making such structure are described. The structure uses a combination of recessed oxide isolation with pairs of parallel, anisotropic etched trenches which are subsequently oxidized and filled to give complete dielectric isolation for regions of monocrystalline silicon. The anisotropic etching preferably etches a buried N+ sublayer under the mnocrystalline silicon region and then the trench structure is thermally oxidized to consume the remaining N+ layer under the monocrystalline region and to fully isolate the monocrystalline silicon region between pairs of such trenches.

Total dielectric isolation for integrated circuits

A process for making high performance NPN bipolar transistors functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon body. The transistor includes an N+ subcollector, and N+ collector reach-through which connects the subcollector to a major surface of the silicon body, a P base region above the subcollector and adjacent to the reach-through an N+ emitter region within the base region and extending from the major surface. The base region includes an intrinsic base region located below the emitter region and an extrinsic region extending from the major surface and adjacent to the emitter region. The extrinsic base completely surrounds the emitter region. A mask is formed above the major surface having openings only above major portions of the extrinsic base regions. A P+ region is formed in the extrinsic base region by ion implanting with a P type dopant to a depth less than the depth of the N emitter region followed by a short thermal anneal to activate the P dopant. Electrical ohmic contacts are made and the elements are connected in a current switch logic circuit. The use of high conductivity P+ region in the extrinsic base region closely adjacent to the emitter reduces the extrinsic base resistance. Independent doping in the extrinsic base through the mask openings allows independent control of the intrinsic and extrinsic base resistances. These changes increase the performance of bipolar transistor integrated circuits for current switch logic applications.

Method for making a high performance transistor integrated circuit

A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization.

Method and resulting structure for selective multiple base width

A fully isolated dielectric structure for isolating regions of monocrystalline silicon from one another and method for making such structure are described. The structure uses a combination of recessed oxide isolation with pairs of parallel, anisotropic etched trenches which are subsequently oxidized and filled to give complete dielectric isolation for regions of monocrystalline silicon. The anisotropic etching preferably etches a buried N+ sublayer under the monocrystalline silicon region and then the trench structure is thermally oxidized to consume the remaining N+ layer under the monocrystalline region and to fully isolate the monocrystalline silicon region between pairs of such trenches.

A process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The bipolar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitter is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter is etched. and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth. The transistor characteristics depend strongly upon the base width so the etching is controlled to very tight dimensions.

Method for making a base etched transistor integrated circuit

The present invention provides a method for planarizing a non-uniform thickness of oxide, for example silicon dioxide as is formed over oxide-filled trenches used in deep dielectric isolation in integrated circuits. The oxide is removed by a planarizing resist-etching process so that etching in thicker resist areas proceeds at a rate slower than etching in thinner resist areas. A referred etchant is HF gas and etching is preferably at an elevated temperature.

Method of planarizing silicon dioxide in semiconductor devices

Isolating the anode shield of RF sputtering apparatus from the ground potential reduces the grounded surfaces to which the plasma is exposed and thereby increases the impedance between the plasma and the grounded surfaces. This improvement increases the resputtering rate significantly before the operating point of instability in the system is reached.

RF sputtering apparatus having floating anode shield

A method for forming coplanar thin films, particularly conductor-insulator patterns, on a substrate. A pattern which includes a first thin film and an expendable material deposited thereon is formed on the substrate. The expendable material is selected so that it can be selectively removed by an etchant which does not attack the first thin film or an insulator which is to be deposited. The second thin film is deposited by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the second film. This results in the covering of the exposed substrate surfaces and the upper surface of the material with the second film but leaving the side surfaces of the material exposed. The expendable material is then chemically etched so as to lift-off both the material and the second film deposited thereon, thereby leaving a coplanar pattern of first and second thin films. In the preferred embodiment, the first thin film is a conductor and the RF sputtered second thin film is an insulator such as glass. Alternatively, the first thin film could be the insulator with the RF sputtered second film being the conductor, or both thin films could be dissimilar metals or insulators.

Structure for making coplanar layers of thin films

A method for forming coplanar thin films, particularly conductor-insulator patterns, on a substrate. A pattern which includes a first thin film and an expendable material deposited thereon is formed on the substrate. The expendable material is selected so that it can be selectively removed by an etchant which does not attack the first thin film or an insulator which is to be deposited. The second thin film is deposited by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the second film. This results in the covering of the exposed substrate surfaces and the upper surface of the material with the second film but leaving the side surfaces of the material exposed. The expendable material is then chemically etched so as to lift-off both the material and the second film deposited thereon, thereby leaving a coplanar pattern of first and second thin films. In the preferred embodiment, the first thin film is a conductor and the RF sputtered second thin film is an insulator such as glass. Alternatively, the first thin film could be the insulator with the RF sputtered second film being the conductor, or both thin films could be dissimilar metals or insulators. Via hole studs, or feedthroughs, which are metallic interconnections between a first level conductive pattern (metallization) and a second level conductive pattern, may be formed by repeating substantially the same steps atop the first conductive pattern at desired locations. As many substantially coplanar levels as desired may be formed without the need for etching the second thin film.

Making coplanar layers of thin films

A method for forming feedthrough connections, or via studs, between levels of metallization atop semiconductor substrates. A first level conductive pattern is formed atop the substrate. A feedthrough pattern is then formed atop the first conductive pattern, the feedthrough pattern including one or more metal studs and a second, expendable material disposed on the studs. The formation of the feedthrough pattern is preferably accomplished by a lift-off process. The expendable material is removable by an etchant which does not substantially attack either the metal or the substrate. An insulator is deposited atop the substrate and the pattern by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the insulator, thereby covering the exposed substrate surfaces and the expendable material but leaving the side surfaces of the material exposed. The expendable material is then etched with said etchant, thereby removing the second material and the portion of the insulator disposed thereon. A second conductive pattern may then be formed atop the insulator and selectively connected to the feedthroughs which thereby provide the interconnection between the first and second levels.

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Wappingers Falls, NY, United States of America

John S Lechaton